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參數(shù)資料
| 型號： | GS4576S09L-25 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | DDR DRAM, PBGA144 |
| 封裝： | UBGA-144 |
| 文件頁數(shù)： | 38/64頁 |
| 文件大小： | 2691K |
| 代理商： | GS4576S09L-25 |
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Preliminary
GS4576S09/18L
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 4/2011
43/64
2011, GSI Technology
AC Differential Input Clock Levels
Parameter
Symbol
Min.
Max.
Unit
Notes
Clock input differential voltage: CK and CK
VID(AC)
0.4
VDDQ + 0.6
V
1–5
Clock input crossing point voltage: CK and CK
VIX(AC)
VDDQ/2 – 0.15
VDDQ/2 + 0.15
V
1–4, 6
Notes:
1. DKx and DKx have the same requirements as CK and CK.
2. All voltages referenced to VSS (GND).
3. The CK and CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross. The input reference level for
signals other than CK/CK is VREF.
4. The CK and CK input slew rate must be
≥ 2 V/ns (≥ 4 V/ns if measured differentially).
5. VID is the magnitude of the difference between the input level on CK and the input level on CK.
6. The value of VIX is expected to equal VDDQ/2 of the transmitting device and must track variations in the DC level of the same.
VIN(DC) MAX
CK
VDDQ/2 + 0.15
VDDQ/2
VDDQ/2 – 0.15
VIN(DC) MIN
VIX(AC)MAX
VIX(AC)MIN
Maximum Clock Level
Minimum Clock Level
VID(AC)3
VID(DC)2
1
Differential Clock Input Requirements
Notes:
1. CK and CK must cross within this region.
2. CK and CK must meet at least VID(DC)MIN when static and centered around VDDQ/2.
3. Minimum peak-to-peak swing.
4. It is a violation to tristate CK and CK after the part is initialized.
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