參數(shù)資料
型號: GS4576S09L-25
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: DDR DRAM, PBGA144
封裝: UBGA-144
文件頁數(shù): 28/64頁
文件大?。?/td> 2691K
代理商: GS4576S09L-25
576Mb Address Mapping in Multiplexed Address Mode
Data Width
Burst
Length
Ball
Address
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
x18
2
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ay
A20
A1
A2
X
A6
A7
A19
A11
A12
A16
A15
4
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ay
X
A1
A2
X
A6
A7
A19
A11
A12
A16
A15
8
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ay
X
A1
A2
X
A6
A7
X
A11
A12
A16
A15
x9
2
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ay
A20
A1
A2
A21
A6
A7
A19
A11
A12
A16
A15
4
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ay
A20
A1
A2
X
A6
A7
A19
A11
A12
A16
A15
8
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ay
X
A1
A2
X
A6
A7
A19
A11
A12
A16
A15
Notes:
X= Don’t Care.
Preliminary
GS4576S09/18L
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 4/2011
34/64
2011, GSI Technology
Configuration in Mulitplexed Mode
In Multiplexed Address mode, the Read and Write latencies are increased by one clock cycle. However, the LLDRAM II cycle
time remains the same as when in Nonmultiplexed Address mode.
Cycle Time and Read/Write Latency Configuration in Mulitplexed Mode
Parameter
Configuration
Units
13
2
3
43, 4
5
tRC
4
6
8
3
5
tCK
tRL
5
7
9
4
6
tCK
tWL
6
8
10
5
7
tCK
Valid Frequency Range
266–175
400–175
533–175
200–175
333–175
MHz
Notes:
1. tRC < 20 ns in any configuration is only available with –24 and –18 speed grades.
2. Minimum operating frequency for –18 is 370 MHz.
3. BL = 8 is not available.
4. The minimum tRC is typically 3 cycles, except in the case of a Write followed by a Read to the same bank. In this instance the minimum tRC
is 4 cycles.
相關(guān)PDF資料
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GS54180RK 1 ELEMENT, 18 uH, GENERAL PURPOSE INDUCTOR, SMD
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