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參數(shù)資料
| 型號： | GS4576S09L-25 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | DDR DRAM, PBGA144 |
| 封裝： | UBGA-144 |
| 文件頁數(shù)： | 52/64頁 |
| 文件大小： | 2691K |
| 代理商： | GS4576S09L-25 |
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Selection
circuitry
Selection
circuitry
TDO
TDI
Bypass Regsiter
Instruction Regsiter
Identification Regsiter
Boundary Scan Regsiter
TCK
TMS
TAP Controller
Note:
x= 112 for all configurations
Preliminary
GS4576S09/18L
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 4/2011
56/64
2011, GSI Technology
TAP Controller Block Diagram
Performing a TAP RESET
A reset is performed by forcing TMS High (VDDQ) for five rising edges of TCK. This RESET does not affect the operation of the
LLDRAM II and may be performed while the LLDRAM II is operating.
At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the LLDRAM II test
circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK.
Instruction Register
Eight-bit instructions can be serially loaded into the instruction register. This register is loaded during the Update-IR state of the
TAP controller. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described in the previous section.
When the TAP controller is in the Capture-IR state, the two LSBs are loaded with a binary “01” pattern to allow for fault isolation
of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is
a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the LLDRAM II with
minimal delay. The bypass register is set Low (VSS) when the BYPASS instruction is executed.
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