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參數(shù)資料
| 型號： | GS4576S09L-25 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | DDR DRAM, PBGA144 |
| 封裝： | UBGA-144 |
| 文件頁數(shù)： | 37/64頁 |
| 文件大?。?/td> | 2691K |
| 代理商： | GS4576S09L-25 |
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Preliminary
GS4576S09/18L
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 4/2011
42/64
2011, GSI Technology
DC Differential Input Clock Logic Levels
Parameter
Symbol
Min.
Max.
Unit
Notes
Clock input voltage level: CK and CK
VIN(DC)
–0.3
VDDQ + 0.3
V
1–4
Clock input differential voltage: CK and CK
VID(DC)
0.2
VDDQ + 0.6
V
1–5
Notes:
1. DKx and DKx have the same requirements as CK and CK.
2. All voltages referenced to VSS (GND).
3. The CK and CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross. The input reference level for
signals other than CK/CK is VREF.
4. The CK and CK input slew rate must be
≥ 2 V/ns (≥ 4 V/ns if measured differentially).
5. VID is the magnitude of the difference between the input level on CK and the input level on CK.
Recommended AC Operating Conditions and Electrical Characteristics
Input AC Logic Levels
Parameter
Symbol
Min.
Max.
Unit
Notes
Input High (logic 1) Voltage
VIH
VREF + 0.2
—
V
1, 2, 3
Input Low (logic 0) Voltage
VIL
—
VREF – 0.2
V
1, 2, 3
Notes:
1. All voltages referenced to VSS (GND).
2. The AC and the DC input level specifications are defined in the HSTL standard (that is, the receiver will effectively switch as a result of the
signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above (see drawing below) the DC
input Low (High) level).
3. The minimum slew rate for the input signals used to test the device is 2 V/ns in the range between VIL(AC) and VIH(AC).
VIH(DC)MIN
VREF
VIL(DC)MAX
VDDQ
VIH(AC)MIN
VIL(AC)MAX
VSSQ
V
SWING(AC)
(M
IN
)
Nominal tAS/ tCS/ tDS and tAH/ tCH/ tDH Slew Rate
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