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參數(shù)資料
| 型號： | GS4576S09L-25 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | DDR DRAM, PBGA144 |
| 封裝： | UBGA-144 |
| 文件頁數(shù)： | 34/64頁 |
| 文件大?。?/td> | 2691K |
| 代理商： | GS4576S09L-25 |
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Preliminary
GS4576S09/18L
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 4/2011
4/64
2011, GSI Technology
Ball Descriptions
Symbol
Type
Description
A0–A21
Input
Address Inputs—A0–A21 define the row and column addresses for Read and Write Operations. During
a Mode Register Set (MRS), the address inputs define the register settings. They are sampled at the
rising edge of CK.
BA0–B2
Input
Bank Address inputs—Select to which internal bank a command is being applied.
CK, CK
Input
Input Clock—CK and CK are differential input clocks. Addresses and commands are latched on the
rising edge of CK. CK is ideally 180 out of phase with CK.
CS
Input
Chip Select—CS enables the command decoder when Low and disables it when High. When the
command decoder is disabled, new commands are ignored, but internal operations continue.
D0–D17
Input
Data Input—The D signals form the 18-bit input data bus. During Write commands, the data is sampled
at both edges of DK.
DK, DK
Input
Input Data Clock—DK and DK are the differential input data clocks. All input data is referenced to both
edges of DK. DK is ideally 180 out of phase with DK. In both the x9 and x18 devices, all Ds are
referenced to DK and DK.
DM
Input
Input Data Mask—The DM signal is the input mask signal for Write data. Input data is masked when DM
is sampled High. DM is sampled on both edges of DK. Tie signal to ground if not used.
TCK
Input
IEEE 1149.1 clock input—This ball must be tied to VSS if the JTAG function is not used.
TMS, TDI
Input
IEEE 1149.1 test inputs—These balls may be left as no connects if the JTAG function is not used.
WE, REF
Input
Command Inputs—Sampled at the positive edge of CK, WE and REF define (together with CS) the
command to be executed.
VREF
Input
Input Reference Voltage—Nominally VDDQ/2. Provides a reference voltage for the input buffers.
ZQ
I/O
External Impedance (25–60
Ω)—This signal is used to tune the device outputs to the system data bus
impedance. Q output impedance is set to 0.2 * RQ, where RQ is a resistor from this signal to ground.
Connecting ZQ to GND invokes the Minimum Impedance mode. Connecting ZQ to VDD invokes the
maximum Impedance mode. Refer to the Mode Register Definition diagrams (Mode Register Bit 8 (M8))
to activate or deactivate this function.
Q0–Q17
Output
Data Output—The Q signals form the 18-bit output data bus. During Read commands, the data is
referenced to both edges of QK.
QKx, QKx
Output
Output Data Clocks—QKx and QKx are opposite polarity, output data clocks. They are free running,
and during Reads, are edge-aligned with data output from the LLDRAM II. QKx is ideally 180 out of
phase with QKx. For the x18 device, QK0 and QK0 are aligned with Q0–Q8, while QK1 and QK1 are
aligned with Q9–Q17. For the x9 device, all Qs are aligned with QK0 and QK0.
QVLD
Output
Data Valid—The QVLD pin indicates valid output data. QVLD is edge-aligned with QKx and QKx.
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| GS4576S18GL-24I | 制造商:GSI Technology 功能描述:32MB X 18 SEPARATE I/O - Trays |
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| GS4-6 | 制造商:JST Manufacturing 功能描述:CRIMP TERMINAL RING 4MM 制造商:JST Manufacturing 功能描述:CRIMP TERMINAL, RING, 4MM 制造商:JST Manufacturing 功能描述:CRIMP TERMINAL, RING, 4MM; Connector Type:Ring Tongue; Termination Method:Crimp; Stud/Tab Size:4mm; Wire Size AWG Min:12AWG; Wire Size AWG Max:10AWG; SVHC:No SVHC (19-Dec-2012); Cable Diameter Max:3.6mm; Stud Size:4mm; Wire Area Size;RoHS Compliant: Yes |
| GS4-6 BR TIN | 制造商:STIMPSON 功能描述: |
| GS4-6 BRASS | 制造商:STIMPSON 功能描述: |
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