- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄223860 > GS4576S09L-25 (GSI TECHNOLOGY) DDR DRAM, PBGA144 PDF資料下載
參數(shù)資料
| 型號： | GS4576S09L-25 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | DDR DRAM, PBGA144 |
| 封裝： | UBGA-144 |
| 文件頁數(shù)： | 30/64頁 |
| 文件大?。?/td> | 2691K |
| 代理商： | GS4576S09L-25 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當(dāng)前第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
Preliminary
GS4576S09/18L
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 4/2011
36/64
2011, GSI Technology
Read Command in Multiplexed Mode
Address Multiplexed Read data transfers are launched with a Read command, as shown below. A valid address must be provided
during the READ command. The Ax address must be loaded on the same True clock crossing used to load the READ command
and the Bank address. The Ay address and a NOP command must be provided at the next clock crossing.
Each beat of a Read data transfer is edge-aligned with the QKx signals. After a programmable Read Latency, data is available at
the outputs. One half clock cycle prior to valid data on the read bus, the data valid signal (QVLD) is driven High. QVLD is also
edge-aligned with the QKx signals. The QK clocks are free-running.
The skew between QK and the crossing point of CK is specified as tCKQK. tQKQ0 is the skew between QK0 and the last valid
data edge generated at the Q signals associated with QK0 (tQKQ0 is referenced to Q0–Q8). tQKQ1 is the skew between QK1 and
the last valid data edge generated at the Q signals associated with QK1 (tQKQ1 is referenced to Q9–Q17). tQKQx is derived at
each QKx clock edge and is not cumulative over time. tQKQ is defined as the skew between either QK differential pair and any
output data edge.
At the end of a burst transfer, assuming no other commands have been initiated, output data (Q) will go High–Z. The QVLD signal
transitions Low on the beat of a Read burst. Note that if CK/CK violates the VID(DC) specification while a Read burst is occurring,
QVLD remains High until a dummy Read command is issued. Back-to-back Read commands are possible, producing a continuous
flow of output data.
The data valid window specification is referenced to QK transitions and is defined as: tQHP – (tQKQ [MAX] + |tQKQ [MIN]|). See
the Read Data Valid Window section.
Any Read transfer may be followed by a subsequent Write command. The Read-to-Write timing diagram illustrates the timing
requirements for a Read followed by a Write.
Read Command in Mulitplexed Mode
READ
Ax
Ay
BA
CK
CS
WE
REF
ADDRESS
BANK ADDRESS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS54180RK | 1 ELEMENT, 18 uH, GENERAL PURPOSE INDUCTOR, SMD |
| GS54180RJ | 1 ELEMENT, 18 uH, GENERAL PURPOSE INDUCTOR, SMD |
| GS54180BL | 1 ELEMENT, 18 uH, GENERAL PURPOSE INDUCTOR, SMD |
| GS54151RL | 1 ELEMENT, 150 uH, GENERAL PURPOSE INDUCTOR, SMD |
| GS54151RK | 1 ELEMENT, 150 uH, GENERAL PURPOSE INDUCTOR, SMD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS4576S18GL-24I | 制造商:GSI Technology 功能描述:32MB X 18 SEPARATE I/O - Trays |
| GS4576S18L-24I | 制造商:GSI Technology 功能描述:32MB X 18 SEPARATE I/O - Trays |
| GS4-6 | 制造商:JST Manufacturing 功能描述:CRIMP TERMINAL RING 4MM 制造商:JST Manufacturing 功能描述:CRIMP TERMINAL, RING, 4MM 制造商:JST Manufacturing 功能描述:CRIMP TERMINAL, RING, 4MM; Connector Type:Ring Tongue; Termination Method:Crimp; Stud/Tab Size:4mm; Wire Size AWG Min:12AWG; Wire Size AWG Max:10AWG; SVHC:No SVHC (19-Dec-2012); Cable Diameter Max:3.6mm; Stud Size:4mm; Wire Area Size;RoHS Compliant: Yes |
| GS4-6 BR TIN | 制造商:STIMPSON 功能描述: |
| GS4-6 BRASS | 制造商:STIMPSON 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。