參數(shù)資料
型號(hào)： GS4576S09L-25
廠商： GSI TECHNOLOGY
元件分類(lèi)： DRAM
英文描述： DDR DRAM, PBGA144
封裝： UBGA-144
文件頁(yè)數(shù)： 32/64頁(yè)
文件大?。?/td> 2691K
代理商： GS4576S09L-25
Preliminary
GS4576S09/18L
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 4/2011
38/64
2011, GSI Technology
Refresh Commands in Multiplexed Address Mode
The AREF command launches a REFRESH cycle on one row in the bank addressed. Refresh row addresses are generated by an
internal refresh counter. so address inputs are Don’t Care, but Bank addresses (BA 2:0) must be provided during the AREF
command. A refresh may be continuing in one bank while other commands, including other AREF commands, are launched in
other banks. The delay between the AREF command and a READ, WRITE or AREF command to the same bank must be at least
t
RC.
The entire memory must be refreshed every 32 ms (tREF). This means that this 576Mb device requires 128K refresh cycles at an
average periodic interval of 0.24
μs MAX (actual periodic refresh interval is 32 ms/16K rows/8 = 0.244μs). To improve efficiency,
eight AREF commands (one for each bank) can be launched at periodic intervals of 1.95
μs (32 ms/16K rows = 1.95μs). The Auto
Refresh Cycle diagram illustrates an example of a refresh sequence.
Unlike READ and WRITE commands in Address Multiplex mode, all the information needed to execute an AREF command (the
AREF command and the Band Address (BA 2:0)) is loaded in a single clock crossing, another AREF command (to a different
bank) may be loaded on the next clock crossing.
Consecutive Refresh Operations with Multiplexed Mode
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
AC1
NOP
AREF
AC1
NOP
Ax
Ay
Ax
Ay
BAn
BA0
BA1
BA2
BA3
BA4
BA5
BA6
BA7
BAn
CK
CMD
ADDR
BA
Notes:
1.
Any command.
2. Bank n is chosen so that tRC is met.
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