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參數(shù)資料
| 型號： | GS4576S09L-25 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | DDR DRAM, PBGA144 |
| 封裝： | UBGA-144 |
| 文件頁數(shù)： | 46/64頁 |
| 文件大小： | 2691K |
| 代理商： | GS4576S09L-25 |
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Preliminary
GS4576S09/18L
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 4/2011
50/64
2011, GSI Technology
Refresh
Average Periodic Refresh
Interval
tREFI
—
0.24
—
0.24
—
0.24
—
0.24
μ
10
Notes:
1. All timing parameters are measured relative to the crossing point of CK/CK, DK/DK and to the crossing point with VREF of the command,
address, and data signals.
2. Outputs measured with equivalent load:
VTT
50
Ω
Test Point
10 pF
Q
3. Tests for AC timing IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the
related specifications and device operations are tested for the full voltage range specified.
4. AC timing may use a VIL– to–VIH swing of up to 1.5 V in the test environment, but input timing is still referenced to VREF (or to the crossing
point for CK/CK), and parameter specifications are tested for the specified AC input levels under normal use conditions. The minimum slew
rate for the input signals used to test the device is 2 V/ns in the rance between VIL(AC) and VIH(AC).
5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
6. Frequency drift is not allowed.
7. tQKQ0 is referenced to Q0–Q8. tQKQ1 is referenced to Q9–Q17.
8. tQKQ takes in to account the skew between any QKx and any Q.
9. tDVW (MIN)
≤ tQHP – (tQKQx [MAX] + |tQKQx [MIN]|)
10. To improve efficiency, eight AREF commands (one for each bank) can be posted to the LLDRAM II on consecutive cycles at periodic
intervals of 1.95
μs.
AC Electrical Characteristics (Continued)
Parameter
Symbol
–18
–24
–25
–33
Un
its
No
tes
Min
Max
Min
Max
Min
Max
Min
Max
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