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參數(shù)資料
| 型號： | EPF8482A |
| 英文描述： | Programmable Logic |
| 中文描述： | 可編程邏輯 |
| 文件頁數(shù)： | 48/61頁 |
| 文件大?。?/td> | 979K |
| 代理商： | EPF8482A |
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Altera Corporation
FLEX 8000 Programmable Logic Device Family Data Sheet
Operating Modes
The FLEX 8000 architecture uses SRAM elements that require
configuration data to be loaded whenever the device powers up and
begins operation. The process of physically loading the SRAM
programming data into the device is called configuration. During
initialization, which occurs immediately after configuration, the device
resets registers, enables I/O pins, and begins to operate as a logic device.
The I/O pins are tri-stated during power-up, and before and during
configuration. The configuration and initialization processes together are
called command mode; normal device operation is called user mode.
SRAM elements allow FLEX 8000 devices to be reconfigured in-circuit
with new programming data that is loaded into the device. Real-time
reconfiguration is performed by forcing the device into command mode
with a device pin, loading different programming data, reinitializing the
device, and resuming user-mode operation. The entire reconfiguration
process requires less than 100 ms and can be used to dynamically
reconfigure an entire system. In-field upgrades can be performed by
distributing new configuration files.
Conguration Schemes
The configuration data for a FLEX 8000 device can be loaded with one of
six configuration schemes, chosen on the basis of the target application.
Both active and passive schemes are available. In the active configuration
schemes, the FLEX 8000 device functions as the controller, directing the
loading operation, controlling external EPROM devices, and completing
the loading process. The clock source for all active configuration schemes
is an oscillator on the FLEX 8000 device that operates between 2 MHz and
6 MHz. In the passive configuration schemes, an external controller
guides the FLEX 8000 device. Table 14 shows the data source for each of
the six configuration schemes.
Table 14. Data Source for Configuration
Configuration Scheme
Acronym
Data Source
Active serial
AS
Altera Configuration EPROM
Active parallel up
APU
Parallel EPROM
Active parallel down
APD
Parallel EPROM
Passive serial
PS
Serial data path
Passive parallel synchronous
PPS
Intelligent host
Passive parallel asynchronous
PPA
Intelligent host
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相關(guān)代理商/技術(shù)參數(shù) |
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| EPF8636A | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Programmable Logic Device Family |
| EPF8636AGC192-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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| EPF8636AGC192-4 | 制造商:Altera Corporation 功能描述:Field-Programmable Gate Array, 504 Cell, 192 Pin, Ceramic, PGA |
| EPF8636AGC192-5 | 制造商:Altera Corporation 功能描述:Field-Programmable Gate Array, 504 Cell, 192 Pin, Ceramic, PGA |
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