參數(shù)資料
型號： EPF8482A
英文描述： Programmable Logic
中文描述： 可編程邏輯
文件頁數(shù)： 10/61頁
文件大?。?/td> 979K
代理商： EPF8482A
18
Altera Corporation
FLEX 8000 Programmable Logic Device Family Data Sheet
Figure 9. FLEX 8000 Device Interconnect Resources
Each LAB is named according to its physical row (A, B, C, etc.) and column (1, 2, 3, etc.) position within the device.
I/O Element
An IOE contains a bidirectional I/O buffer and a register that can be used
either as an input register for external data that requires a fast setup time,
or as an output register for data that requires fast clock-to-output
performance. IOEs can be used as input, output, or bidirectional pins. The
MAX+PLUS II Compiler uses the programmable inversion option to
automatically invert signals from the row and column interconnect where
appropriate. Figure 10 shows the IOE block diagram.
IOE
LAB
A1
LAB
A2
LAB
B1
LAB
B2
LAB Local
Interconnect
Column
Interconnect
Row
Interconnect
Cascade &
Carry Chain
IOE
See Figure 10
for details.
See Figure 11
for details.
1
8
1
8
1
8
IOE
1
8
IOE
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPF8636A 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Programmable Logic Device Family
EPF8636AGC192-2 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EPF8636AGC192-3 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EPF8636AGC192-4 制造商:Altera Corporation 功能描述:Field-Programmable Gate Array, 504 Cell, 192 Pin, Ceramic, PGA
EPF8636AGC192-5 制造商:Altera Corporation 功能描述:Field-Programmable Gate Array, 504 Cell, 192 Pin, Ceramic, PGA
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