參數(shù)資料
型號: EPF8482A
英文描述: Programmable Logic
中文描述: 可編程邏輯
文件頁數(shù): 19/61頁
文件大小: 979K
代理商: EPF8482A
26
Altera Corporation
FLEX 8000 Programmable Logic Device Family Data Sheet
f FordetailedinformationonJTAGoperationinFLEX 8000devices,referto
Generic Testing
Each FLEX 8000 device is functionally tested and specified by Altera.
Complete testing of each configurable SRAM bit and all logic
functionality ensures 100% configuration yield. AC test measurements for
FLEX 8000 devices are made under conditions equivalent to those shown
in Figure 15. Designers can use multiple test patterns to configure devices
during all stages of the production flow.
Table 7. JTAG Timing Parameters & Values
Symbol
Parameter
EPF8282A
EPF8282AV
EPF8636A
EPF8820A
EPF81500A
Unit
Min
Max
tJCP
TCK
clock period
100
ns
tJCH
TCK
clock high time
50
ns
tJCL
TCK
clock low time
50
ns
tJPSU
JTAG port setup time
20
ns
tJPH
JTAG port hold time
45
ns
tJPCO
JTAG port clock to output
25
ns
tJPZX
JTAG port high-impedance to valid output
25
ns
tJPXZ
JTAG port valid output to high-impedance
25
ns
tJSSU
Capture register setup time
20
ns
tJSH
Capture register hold time
45
ns
tJSCO
Update register clock to output
35
ns
tJSZX
Update register high-impedance to valid output
35
ns
tJSXZ
Update register valid output to high-impedance
35
ns
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