參數(shù)資料
型號(hào)： EPF8482A
英文描述： Programmable Logic
中文描述： 可編程邏輯
文件頁(yè)數(shù)： 4/61頁(yè)
文件大?。?/td> 979K
代理商： EPF8482A
12
Altera Corporation
FLEX 8000 Programmable Logic Device Family Data Sheet
Normal Mode
The normal mode is suitable for general logic applications and wide
decoding functions that can take advantage of a cascade chain. In normal
mode, four data inputs from the LAB local interconnect and the carry-in
signal are the inputs to a 4-input LUT. Using a configurable SRAM bit, the
MAX+PLUS II Compiler automatically selects the carry-in or the DATA3
signal as an input. The LUT output can be combined with the cascade-in
signal to form a cascade chain through the cascade-out signal. The LE-Out
signal—the data output of the LE—is either the combinatorial output of
the LUT and cascade chain, or the data output (Q)of the programmable
register.
Arithmetic Mode
The arithmetic mode offers two 3-input LUTs that are ideal for
implementing adders, accumulators, and comparators. One LUT
provides a 3-bit function; the other generates a carry bit. As shown in
Figure 6, the first LUT uses the carry-in signal and two data inputs from
the LAB local interconnect to generate a combinatorial or registered
output. For example, in an adder, this output is the sum of three bits: a, b,
and the carry-in. The second LUT uses the same three signals to generate
a carry-out signal, thereby creating a carry chain. The arithmetic mode
also supports a cascade chain.
Up/Down Counter Mode
The up/down counter mode offers counter enable, synchronous
up/down control, and data loading options. These control signals are
generated by the data inputs from the LAB local interconnect, the carry-in
signal, and output feedback from the programmable register. Two 3-input
LUTs are used: one generates the counter data, and the other generates the
fast carry bit. A 2-to-1 multiplexer provides synchronous loading. Data
can also be loaded asynchronously with the clear and preset register
control signals, without using the LUT resources.
Clearable Counter Mode
The clearable counter mode is similar to the up/down counter mode, but
supports a synchronous clear instead of the up/down control; the clear
function is substituted for the cascade-in signal in the up/down counter
mode. Two 3-input LUTs are used: one generates the counter data, and
the other generates the fast carry bit. Synchronous loading is provided by
a 2-to-1 multiplexer, and the output of this multiplexer is ANDed with a
synchronous clear.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPF8636A 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Programmable Logic Device Family
EPF8636AGC192-2 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EPF8636AGC192-3 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EPF8636AGC192-4 制造商:Altera Corporation 功能描述:Field-Programmable Gate Array, 504 Cell, 192 Pin, Ceramic, PGA
EPF8636AGC192-5 制造商:Altera Corporation 功能描述:Field-Programmable Gate Array, 504 Cell, 192 Pin, Ceramic, PGA
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