參數(shù)資料
型號: EPF8482A
英文描述: Programmable Logic
中文描述: 可編程邏輯
文件頁數(shù): 23/61頁
文件大?。?/td> 979K
代理商: EPF8482A
Altera Corporation
3
FLEX 8000 Programmable Logic Device Family Data Sheet
FLEX
8000
3
FLEX 8000 devices provide a large number of storage elements for
applications such as digital signal processing (DSP), wide-data-path
manipulation, and data transformation. These devices are an excellent
choice for bus interfaces, TTL integration, coprocessor functions, and
high-speed controllers. The high-pin-count packages can integrate
multiple 32-bit buses into a single device. Table 3 shows FLEX 8000
performance and LE requirements for typical applications.
All FLEX 8000 device packages provide four dedicated inputs for
synchronous control signals with large fan-outs. Each I/O pin has an
associated register on the periphery of the device. As outputs, these
registers provide fast clock-to-output times; as inputs, they offer quick
setup times.
The logic and interconnections in the FLEX 8000 architecture are
configured with CMOS SRAM elements. FLEX 8000 devices are
configured at system power-up with data stored in an industry-standard
parallel EPROM or an Altera serial Configuration EPROM device, or with
data provided by a system controller. Altera offers the EPC1, EPC1213,
EPC1064, and EPC1441 Configuration EPROMs, which configure
FLEX 8000 devices via a serial data stream. Configuration data can also be
stored in an industry-standard 32 K
× 8 bit or larger EPROM, or
downloaded from system RAM. After a FLEX 8000 device has been
configured, it can be reconfigured in-circuit by resetting the device and
loading new data. Because reconfiguration requires less than 100 ms, real-
time changes can be made during system operation.
f For information on how to configure FLEX 8000 devices, go to the
following documents:
Table 3. FLEX 8000 Performance
Application
LEs Used
A-2 Speed Grade A-3 Speed Grade
A-4 Speed
Grade
Units
16-bit loadable counter
16
125
95
83
MHz
16-bit up/down counter
16
125
95
83
MHz
24-bit accumulator
24
87
67
58
MHz
16-bit address decode
4
4.2
4.9
6.3
ns
16-to-1 multiplexer
10
6.6
7.9
9.5
ns
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