參數(shù)資料
型號： EPF8482A
英文描述： Programmable Logic
中文描述： 可編程邏輯
文件頁數(shù)： 26/61頁
文件大?。?/td> 979K
代理商： EPF8482A
32
Altera Corporation
FLEX 8000 Programmable Logic Device Family Data Sheet
Timing Model
The continuous, high-performance FastTrack Interconnect routing
structure ensures predictable performance and accurate simulation and
timing analysis. This predictable performance contrasts with that of
FPGAs, which use a segmented connection scheme and hence have
unpredictable performance. Timing simulation and delay prediction are
available with the MAX+PLUS II Simulator and Timing Analyzer, or with
industry-standard EDA tools. The Simulator offers both pre-synthesis
functional simulation to evaluate logic design accuracy and post-
synthesis timing simulation with 0.1-ns resolution. The Timing Analyzer
provides point-to-point timing delay information, setup and hold time
prediction, and device-wide performance analysis.
Tables 8 through 11 describe the FLEX 8000 timing parameters and their
symbols.
Table 8. FLEX 8000 Internal Timing Parameters
Symbol
Parameter
tIOD
IOE register data delay
tIOC
IOE register control signal delay
tIOE
Output enable delay
tIOCO
IOE register clock-to-output delay
tIOCOMB IOE combinatorial delay
tIOSU
IOE register setup time before clock; IOE register recovery time after asynchronous clear
tIOH
IOE register hold time after clock
tIOCLR
IOE register clear delay
tIN
Input pad and buffer delay
tOD1
Output buffer and pad delay, slow slew rate = off, VCCIO = 5.0 V, C1 = 35 pF, Note (2)
tOD2
Output buffer and pad delay, slow slew rate = off, VCCIO = 3.3 V, C1 = 35 pF, Note (2)
tOD3
Output buffer and pad delay, slow slew rate = on, C1 = 35 pF,
tXZ
Output buffer disable delay, C1 = 5 pF
tZX1
Output buffer enable delay, slow slew rate = off, VCCIO = 5.0 V, C1 = 35 pF, Note (2)
tZX2
Output buffer enable delay, slow slew rate = off, VCCIO = 3.3 V, C1 = 35 pF, Note (2)
tZX3
Output buffer enable delay, slow slew rate = on, C1 = 35 pF,
相關(guān)PDF資料
PDF描述
EPIC EPiC Family Product Line (304k)
EPL10P8BD UV-Erasable/OTP PLD
EPL10P8BP UV-Erasable/OTP PLD
EPL12P6BD UV-Erasable/OTP PLD
EPL241ED UV-Erasable/OTP PLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPF8636A 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Programmable Logic Device Family
EPF8636AGC192-2 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EPF8636AGC192-3 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EPF8636AGC192-4 制造商:Altera Corporation 功能描述:Field-Programmable Gate Array, 504 Cell, 192 Pin, Ceramic, PGA
EPF8636AGC192-5 制造商:Altera Corporation 功能描述:Field-Programmable Gate Array, 504 Cell, 192 Pin, Ceramic, PGA
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*