
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name:
RSIGC
Register Description:
Receive Signaling Control Register
Register Address:
base address + 0x04C
Bit #
7
6
5
4
3
2
1
0
Name T1
Name E1
-
RFSA1
CASMS
-
RSFF
-
RSFE
-
RSIE
-
Default
0
Bit 4 (T1 Mode): Rx Force Signaling All Ones (RFSA1). See Section
10.11.3.2.
0 = Do not force robbed bit signaling to all ones on RSER
1 = Force signaling bits on RSER to all ones on a per-channel basis according to the
RSAOI registers.
Bit 4 (E1 Mode): CAS Mode Select (CASMS).
0 = The framer initiates a resync when two consecutive multiframe alignment signals have been received
with an error.
1 = The framer initiates a resync when two consecutive multiframe alignment signals have been received
with an error, OR 1 multiframe has been received with all the bits in timeslot 16 in state 0. Alignment
criteria is met when at least one bit is set to 1 in the timeslot 16 preceding the multiframe alignment
signal first detected (G.732 alternate criteria).
Bit 2: Rx Signaling Force Freeze (RSFF). Freezes Rx side signaling at RSIG (and RSER if Rx Signaling
Reinsertion is enabled). Overrides Rx Freeze Enable (RFE) bit below. See Section
10.11.3.2.
0 = Do not force a freeze event
1 = Force a freeze event
Bit 1: Rx Signaling Freeze Enable (RSFE). See Section
10.11.3.2.
0 = No freezing of Rx signaling data occurs
1 = Allow freezing of Rx signaling data at RSIG (and RSER if Rx signaling reinsertion is enabled).
Bit 0: Rx Signaling Integration Enable (RSIE). See Section
10.11.3.2.
0 = All signaling changes immediately reported with no integration
1 = Signaling must be stable for 3 multiframes before a change is reported
Register Name:
RCR2-T1
Register Description:
Receive Control Register 2 (T1 Mode)
Register Address:
base address + 0x050
Bit #
7
6
5
4
3
2
1
0
Name
-
RSLC96
OOF2
OOF1
RAIIE
RD4RM
Default
0
Note: This register has an alternate definition for E1 mode. See
RSAIMR.Bit 4: Rx SLC-96 Synchronizer Enable (RSLC96). See Section
10.11.16.2 for SLC-96 details.
0 = the SLC-96 synchronizer is disabled
1 = the SLC-96 synchronizer is enabled
Bits 3 to 2: Out-of-Frame Select Bits (OOF[2:1]).
OOF2
OOF1
OUT OF FRAME CRITERIA
0
2 out of 4 frame bits in error
0
1
2 out of 5 frame bits in error
1
0
2 out of 6 frame bits in error
1
2 out of 6 frame bits in error