
DM9102A
Single Chip Fast Ethernet NIC controller
the WOL as pulse or DC signal.
0 = WOL pulse mode (default)
1 = WOL DC mode
BPAD2 is also a reset latch pin. It is Boot ROM address and
data bus when normal operation. When at power on reset, it is
used to pull up or down externally through a resister to select
the PME as pulse or DC signal.
0 = PME pulse mode (default)
1 = PME DC mode
BPAD7 is also a reset latch pin. It is Boot ROM address and
data bus when normal operation. When at power on reset, it is
used to pull up or down externally through a resister to select
LED mode.
0 = LED mode 0 (default)
1 = LED mode 1
72
BPCS#
O
Boot ROM Chip Select
Boot ROM or external register chip select signal.
73
BPA0/WMODE
O, LI
Boot ROM address line/WOL mode selection
This multiplexed pin acts as boot ROM address bit 0 output
signal during normal operation. When at power on reset, it
used to select the type of WOL signal.
0 = WOL high active (default)
1 = WOL low active
74
BPA1/PCIMODE#
I/O, LI Boot ROM address line / PCI mode selection
This multiplexed pin acts as the boot ROM address bit 1 output
signal during normal operation. When RST# is active (low), it
acts as the input system type. If the DM9102A is used in a
CardBus system, this pin should be connected to a pull-up
resistor; otherwise, the DM9102A consider the host as a PCI
system.
0 = PCI mode (default)
1 = CardBus mode
77
EEDI
I
EEPROM Data In
The DM9102A will read the contents of EEPROM serially
through this pin.
78
EEDO
O
EEPROM Data Out
The DM9102A will use this pin to serially write opcodes,
addresses and data into the EEPROM.
79
EECK
O
EEPROM Serial Clock
This pin provides the clock for the EEPROM data transfer.
80
EECS
O
EEPROM Chip Select
This pin will enable the EEPROM during loading of the
Configuration Data.
81
SELROM
I
Multiplex or Director mode selection
0 = Multiplex mode (default)
1 = Direct mode
83,84,85,91,92,93,94
NC
NC
In Multiplex mode, these pins are not connected.
Final
Version: DM9102A-DS-F03
August 28, 2000
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