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參數(shù)資料
| 型號： | DM9102 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Single Chip Fast Ethernet NIC controller |
| 中文描述： | 單芯片快速以太網(wǎng)網(wǎng)卡控制器 |
| 文件頁數(shù)： | 39/77頁 |
| 文件大?。?/td> | 459K |
| 代理商： | DM9102 |
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DM9102A
Single Chip Fast Ethernet NIC controller
Final
Version: DM9102A-DS-F03
August 28, 2000
39
CardBus Status Changed Registers
The DM9102A implements four status changed registers.
These status changed registers are accessed by the
CardBus systom software. These registers are mapped
only to the memory address space and not to the I/O
address space.
1. Function Event Register: (offset 80h)
Bit
0:3
Name
Reserved
Default
R/W
Description
Unpredictable on read
4
General Wake-up
Event
R/WC
This bit is set when the DM9102A has detected a power management event.
This bit is cleared upon power-up reset and by write 1. It is unaffected by either
hardware or software reset. When the PME_Status bit in the PCI configuration is
cleared, this bit is automatically cleared as well.
Unpredictable on read
5:14
Reserved
R/W
15
Interrupt
R/WC
This bit is set when there is an interrupt pending.
This bit is cleared by write 1. This bit is cleared upon hardware or software reset.
Unpredictable on read
16:31
Reserved
R/W
2. Function Event Mask Register: (offset 84h)
Bit
0:3
Name
Reserved
Default
R/W
Description
Unpredictable on read
4
General Wake-up
Event Enable
R/WC
When set together with the Wake-up Event Summary Enable bit (Function Event
Mask Register<14>), enables the assertion of the CSTSCHG pin.
To disable the assertion of the CSTSCHG, the PME_Enable bit in the PCI
configuration register (PMC<8>) must be cleared as well.
This bit is cleared upon power up reset.
Unpredictable on read
5:13
Reserved
R/W
14
Wake-up Event
Summary Enable
R/W
When set together with the General Wake-up Event Enable bit (Function Event
Mask Register<4>), enables the assertion of the CSTSCHG pin.
To disable the assertion of the CSTSCHG pin, the PME_Enable bit in the PCI
configuration register (PMC<8>) must be cleared as well.
This is cleared upon power up reset.
When set, enable the assertion of the interrupt pin (INT#).
This bit is cleared upon hardware or software reset.
Unpredictable on read
15
Interrupt Register
Enable
Reserved
R/W
16:31
R/W
3. Function Present State Register: (offset 88h)
Bit
0:3
Name
Reserved
Default
R/W
Description
Unpredictable on read
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DM9102A | Single Chip Fast Ethernet NIC controller |
| DM9102AF | Single Chip Fast Ethernet NIC controller |
| DM9102AT | Single Chip Fast Ethernet NIC controller |
| DM9108APPLICATIONENGINEERINGNOTESONE | DM9108 Application Engineering notes one |
| DM9108APPLICATIONENGINEERINGNOTESTHREE | DM9108 Application Engineering notes three |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM9102A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single Chip Fast Ethernet NIC controller |
| DM9102AF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single Chip Fast Ethernet NIC controller |
| DM9102AT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single Chip Fast Ethernet NIC controller |
| DM9102D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE CHIP FAST ETHEMET NIC CONTROLLER |
| DM9102DE | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller |
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