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參數(shù)資料
| 型號： | DM9102 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Single Chip Fast Ethernet NIC controller |
| 中文描述： | 單芯片快速以太網(wǎng)網(wǎng)卡控制器 |
| 文件頁數(shù)： | 31/77頁 |
| 文件大?。?/td> | 459K |
| 代理商： | DM9102 |
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DM9102A
Single Chip Fast Ethernet NIC controller
15:14
TSB
0,RW
Threshold Bits
These bits are set together with CR6<22> (chose 10Mb or 100Mb) and will decide
the exact FIFO threshold level. The packet transmission will start after the data level
exceeds the threshold value.
Bit15 Bit14 Threshold(100M) Threshold(10M)
0 0 128 72
0 1 256 96
1 0 512 128
1 1 Reserved Reserved
13
TXSC
0,RW
Transmit Start/stop Command
When set, transmit process will begin by fetching the transmit descriptor for
available packet data to be transmitted (running state). If the fetched descriptor is
owned by the host, transmit process will enter the suspend state and transmit buffer
unavailable (CR5<2>) is set. Otherwise it will begin to move data from host to
FIFO and transmit out after reaching threshold level.
When reset, transmit process is placed in the stopped state after completing the
transmission of the current frame.
12
FCM
0,RW
Force Collision Mode
When set, the transmission process is forced to be the collision status. Meaningful
only in the internal loopback mode.
11:10
LBM
0,RW
Loopback Mode
These bits decide two loopback modes besides normal operation. External
loopback mode expects transmitted data back to receive path and makes no
collision detection.
Final
Version: DM9102A-DS-F03
August 28, 2000
31
Bit11 Bit10 Loopback Mode
0 0 normal
0 1 internal loopback
1 0 internal PHY digital loopback
1 1 internal PHY analog loopback
9
FDM
0,RW
Full-duplex Mode
This bit is set to make DM9102A operate in the full-duplex mode. Transmit and
receive processes can work simultaneously.
There is no collision detection needed during this mode operation.
Must be zero.
Pass All Multicast
When set, any packet with a multicast destination address is received by the
DM9102A. The packet with a physical address will also be filtered based on the
filter mode setting.
Promiscuous mode
When set, any incoming valid frame is received by the DM9102A, and no matter
what the destination address. The DM9102A is initialized to this mode after reset
operation.
Must be Zero.
Inverse Address Filtering Mode
It is set to indicate the DM9102A operate in a Inverse Filtering Mode. This is a read
only bit and mapped from the setup frame together with CR6<2>, CR6<0> setting.
That is, it is valid only during perfect filtering mode.
8
7
Reserved
PAM
0,RO
0,RW
6
PM
1,RW
5
4
Reserved
IAFM
0,RO
0,RO
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DM9102A | Single Chip Fast Ethernet NIC controller |
| DM9102AF | Single Chip Fast Ethernet NIC controller |
| DM9102AT | Single Chip Fast Ethernet NIC controller |
| DM9108APPLICATIONENGINEERINGNOTESONE | DM9108 Application Engineering notes one |
| DM9108APPLICATIONENGINEERINGNOTESTHREE | DM9108 Application Engineering notes three |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM9102A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single Chip Fast Ethernet NIC controller |
| DM9102AF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single Chip Fast Ethernet NIC controller |
| DM9102AT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single Chip Fast Ethernet NIC controller |
| DM9102D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE CHIP FAST ETHEMET NIC CONTROLLER |
| DM9102DE | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller |
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