參數(shù)資料
型號(hào)： DM9102
廠商： Electronic Theatre Controls, Inc.
英文描述： Single Chip Fast Ethernet NIC controller
中文描述： 單芯片快速以太網(wǎng)網(wǎng)卡控制器
文件頁(yè)數(shù)： 30/77頁(yè)
文件大?。?/td> 459K
代理商： DM9102
DM9102A
Single Chip Fast Ethernet NIC controller
This bit is set when the DM9102A fetches the next transmit descriptor that is still
owned by the host. Transmit process will be suspended until the transmit polling
command is set or auto-polling timer time-out.
1
TXPS
0,RW
Transmit Process Stopped
This bit is set to indicate transmit process enters the stopped state.
0
TXCI
0,RW
Transmit Complete Interrupt
This bit is set when a frame is fully transmitted and transmit status has been written to
descriptor (the TDES1<31> is also asserted). Transmit process is still running and
continues to fetch next descriptor.
30
Final
Version: DM9102A-DS-F03
August 28, 2000
7. Network Operation Mode Register (CR6)
Bit
30
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
1
0
0
0
0
0
0
Name
RXA
Default
0,RW
Description
Receive All
When set, all incoming packet will be received, regardless the destination address.
The address match is checked according to theCR6<7>, CR6<6>, CR6<4>,
CR6<2>, CR6<0>, and RDES0<30> will show this match.
Set to not purge RX FIFO if RX buffer unavailable
Must be Zero
Must be One
Must be Zero
Transmit Threshold Mode
When set, the transmit threshold mode is 10Mb/s. When reset, the threshold mode
is 100Mb/s. This bit is used together with CR6<15:14> to decide the exact
threshold level.
Store and Forward Transmit
When set, the packet transmission from MAC will be started after a full frame has
been moved from the host memory to transmit FIFO. When reset, the packet
transmission’s start will depend on the threshold value specified in CR6<15:14>
Start Transmission Immediately
When this bit is set, the packet transmission from MAC will be started immediately
after transmit FIFO’s threshold level reaches 16 bytes, regardless of the setting in
CR6<22> and CR6<15:14>. This mode will make transmit FIFO underrun
condition to happen more easily.
Reserved
1: Select external MII interface.
0: Select external SRL interface.
In external MII mode that the pins TEST1, TEST2, and CLOCKRUN# are forced to
low, the DM9102A bypasses internal PHY and uses external PHY, by setting this
bit properly.
See page 66 for details.
Reserved
One Packet Mode
When this bit is set, only one packet is stored at TX FIFO.
29
NPFIFO
Reserved
Reserved
Reserved
TXTM
0,RW
000,RO
1,RO
00,RO
1,RW
28:26
25
24:23
22
21
SFT
0,RW
20
STI
0,RW
19
18
Reserved
External
MII_Mode
0,RO
1,RW
17
16
Reserved
1pkt
0,RO
0,RW
相關(guān)PDF資料
PDF描述
DM9102A Single Chip Fast Ethernet NIC controller
DM9102AF Single Chip Fast Ethernet NIC controller
DM9102AT Single Chip Fast Ethernet NIC controller
DM9108APPLICATIONENGINEERINGNOTESONE DM9108 Application Engineering notes one
DM9108APPLICATIONENGINEERINGNOTESTHREE DM9108 Application Engineering notes three
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DM9102A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single Chip Fast Ethernet NIC controller
DM9102AF 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single Chip Fast Ethernet NIC controller
DM9102AT 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single Chip Fast Ethernet NIC controller
DM9102D 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE CHIP FAST ETHEMET NIC CONTROLLER
DM9102DE 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller
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