參數(shù)資料
型號： DM9102
廠商： Electronic Theatre Controls, Inc.
英文描述： Single Chip Fast Ethernet NIC controller
中文描述： 單芯片快速以太網(wǎng)網(wǎng)卡控制器
文件頁數(shù)： 32/77頁
文件大?。?/td> 459K
代理商： DM9102
DM9102A
Single Chip Fast Ethernet NIC controller
3
PBF
0,RW
Pass Bad Frame
When set, the DM9102 is indicated to receive the bad frames including runt
packets, truncated frames caused by the FIFO overflow. The bad frame also has to
pass the address filtering if the DM9102A is not set in promiscuous mode.
2
HOFM
0,RO
Hash-only Filter Mode
This is a read-only bit and mapped from the set-up frame together with bit4,0 of
CR6.
It is set to indicate the DM9102A operate in a Hash-only Filtering Mode.
1
RXRC
0,RW
Receive Start/Stop Command
When set, receive process will begin by fetching the receive descriptor for available
buffer to store the new-coming packet (placed in the running state). If the fetched
descriptor is owned by the host (no descriptor is owned by the DM9102A), the
receive process will enter the suspend state and receive buffer unavailable
CR5<7> sets. Otherwise it runs to wait for the packet’s income. When reset,
receive process is placed in the stopped state after completing the reception of the
current frame.
0
HPFM
0,RO
Hash/Perfect Filter Mode
This is a read only bit and mapped from the setup frame together with CR6<4>,
CR6<2>. When reset, the DM9102A does a perfect address filter of incoming
frames according to the addresses specified in the setup frame. When set, the
DM9102A does a imperfect address filtering for the incoming frame with a multicast
address according to the hash table specified in the setup frame. The filtering mode
(perfect / imperfect) for the frame with a physical address will depend on CR6<2>.
32
Final
Version: DM9102A-DS-F03
August 28, 2000
8. Interrupt Mask Register (CR7)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit
16
Name
NISE
Default
0,RW
Description
Normal Interrupt Summary Enable
This bit is set to enable the interrupt for Normal Interrupt Summary.
Normal interrupt includes three conditions :
CR5<0> – TXCI : Transmit Complete Interrupt
CR5<2> – TXDU : Transmit Buffer Unavailable
CR5<6> – RXCI : Receive Complete Interrupt
Abnormal Interrupt Summary Enable
This bit is set to enable the interrupt for Abnormal Interrupt Summary.
Abnormal interrupt includes all interrupt condition as shown below excluding
Normal Interrupt conditions. They are TXPS(bit1), TXJT(bit3), TXFU(bit5),
RXDU(bit7), RXPS(bit8), RXWT(bit9), TXER(bit10), GPT(bit11), SBE(bit13).
Early Receive Interrupt Enable
This bit is set to enable the interrupt for Early Receive.
System Bus Error Enable
When set together with CR7<15>, CR5<13>, it enables the interrupt for System
Bus Error. The type of system bus error is shown in CR5<24:23>.
Link Status Change Interrupt Enable
This bit is set to enable the interrupt for link status change.
15
AISE
0,RW
14
ERIE
0,RW
13
SBEE
0,RW
12
LCIE
0,RW
相關PDF資料
PDF描述
DM9102A Single Chip Fast Ethernet NIC controller
DM9102AF Single Chip Fast Ethernet NIC controller
DM9102AT Single Chip Fast Ethernet NIC controller
DM9108APPLICATIONENGINEERINGNOTESONE DM9108 Application Engineering notes one
DM9108APPLICATIONENGINEERINGNOTESTHREE DM9108 Application Engineering notes three
相關代理商/技術參數(shù)
參數(shù)描述
DM9102A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single Chip Fast Ethernet NIC controller
DM9102AF 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single Chip Fast Ethernet NIC controller
DM9102AT 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single Chip Fast Ethernet NIC controller
DM9102D 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE CHIP FAST ETHEMET NIC CONTROLLER
DM9102DE 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*