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參數(shù)資料
| 型號(hào)： | DM9102 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Single Chip Fast Ethernet NIC controller |
| 中文描述： | 單芯片快速以太網(wǎng)網(wǎng)卡控制器 |
| 文件頁數(shù)： | 26/77頁 |
| 文件大小： | 459K |
| 代理商： | DM9102 |
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DM9102A
Single Chip Fast Ethernet NIC controller
26
Final
Version: DM9102A-DS-F03
August 28, 2000
1. System Control Register (CR0)
Bit
24:22
21
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reserved
MRM
Default
0,RO
0,RW
Description
Reserved
Memory Read Multiple
When set, the DM9102A will use memory read multiple command (C/BE3~0 =
1100) when it initialize the memory read burst transaction as a master device.
When reset, it will use memory read command (C/BE3 ~ 0 = 0110) for the same
master operation.
Reserved
Transmit Automatic polling interval time
When set, the DM9102A will poll transmit descriptor automatically when it is in the
suspend state due to buffer unavailable. The polling interval time is programmable
based on the table shown below.
Bit 19 Bit 18 Bit 17 Time Interval
0 0 0 No polling
0 0 1 200us
0 1 0 800us
0 1 1 1.6ms
1 0 0 12.8us
1 0 1 25.6us
1 1 0 51.2us
1 1 1 102.4us
Reserved
Address Boundary Alignment
When set, the DM9102A will execute each burst cycles to stop at the programmed
address boundary. The address boundary can be programmed to be 8, 16, or 32
doubleword as shown below.
20
Reserved
TXAP
0,RO
000,RW
19:17
16
Reserved
ABA
0,RO
00,RW
15:14
Bit 15 Bit 14 Alignment Boundary
0 0 Reserved
0 1 8-double word
1 0 16-double word
1 1 32-double word
13:8
BL
000000,
RW
Burst Length
When reset, the DM9102A’s burst length in one DMA transfer is limited by the
amount of data in the receive FIFO ( when receive ) or the amount of free space in
the transmit FIFO (when transmit ). When set, the DMA’s burst length is limited by
the programmed value. The permissible values are 0, 1, 2, 4, 8, 16, or 32
doublewords.
Reserved
7
Reserved
Reserved
Reserved
0,RO
00000
0,RO
6:2
1
Reserved
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DM9102A | Single Chip Fast Ethernet NIC controller |
| DM9102AF | Single Chip Fast Ethernet NIC controller |
| DM9102AT | Single Chip Fast Ethernet NIC controller |
| DM9108APPLICATIONENGINEERINGNOTESONE | DM9108 Application Engineering notes one |
| DM9108APPLICATIONENGINEERINGNOTESTHREE | DM9108 Application Engineering notes three |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM9102A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single Chip Fast Ethernet NIC controller |
| DM9102AF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single Chip Fast Ethernet NIC controller |
| DM9102AT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single Chip Fast Ethernet NIC controller |
| DM9102D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE CHIP FAST ETHEMET NIC CONTROLLER |
| DM9102DE | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller |
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