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參數(shù)資料
| 型號： | DDP3300A |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 英文描述： | Single-Chip Display and Deflection Processor |
| 中文描述： | 單芯片顯示器和偏轉(zhuǎn)處理器 |
| 文件頁數(shù)： | 9/53頁 |
| 文件大?。?/td> | 1767K |
| 代理商： | DDP3300A |
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PRELIMINARY DATA SHEET
DDP 3300 A
MICRONAS INTERMETALL
9
2.1.5. Digital Brightness Adjustment
The DC-level of the luminance signal can be adjusted by
adding an 8-bit number in the luminance signal path in
front of the softlimiter.
With a contrast adjustment of 32 (gain
be shifted by
100%. After the brightness addition, the
negative going signals are limited to zero. It is desirable
to keep a small positive offset with the signal to prevent
undershoots produced by the peaking from being cut.
The digital brightness adjustment is separate for main
and side picture.
1) the signal can
2.1.6. Soft Limiter
The dynamic range of the processed luma signal must
be limited to prevent the CRT from overload. An appro-
priate headroom for contrast, peaking and brightness
can be adjusted by the TV manufacturer according to the
CRT characteristics. All signals above this limit will be
‘soft’-clipped. A characteristic diagram of the soft limiter
is shown in Fig. 2–5. The total limiter consists of three
parts:
Part 1 includes adjustable tilt point and gain. The gain
before the tilt value is 1. Above the tilt value, a part
(0...15/16) of the input signal is subtracted from the input
signal itself. Therefore the gain is adjustable from 16/16
to 1/16, when the slope value varies from 0 to 15. The
tilt value can be adjusted from 0 to 511.
Part 2 has the same characteristics as part 1. The sub-
tracting part is also relative to the input signal, so the
total differential gain will become negative if the sum of
slope 1 and slope 2 is greater than 16 and the input sig-
nal is above the both tilt values (see characteristics).
Finally, the output signal of the soft limiter will be clipped
by a hard limiter adjustable from 256 to 511.
Fig. 2–5:
Characteristic of soft limiter a and b and hard limiter
Output
511
Limiter Input
1023
0
2
4
6
8
10
12
14
0
2
4
6
8
10
12
14
slope 1 [0...15]
slope 2 [0...15]
Part 1
Part 2
Hard limiter
tilt 1 [ 0...511]
tilt 2 [0...511]
range= 256...511
0
0
Calculation Example for the
Softlimiter Input Amplitude.
(The real signal processing in
the limiter is 2 bit more than
described here)
Y Input
Black Level
16...235 (ITUR)
16 (constant)
Contrast
Dig. Brightness
BLE
Peaking
63
20
off
off
Limiter input signal:
(Yin–Black Level)·Contr./32 + Brightn.
(235–16) · 63/32 + 20 = 451
100
200
300
400
500
600
700
800
900
100
200
300
400
2.1.7. Chroma Input
The chroma input signal is typically a multiplexed C
R
and
C
B
signal in 8-bit two’s complement code. It can be
switched between normal or inverted signal and be-
tween two’s complement or binary offset (straight
binary) code. Also the delay can be adjusted in 5 steps
within a range of
2 clock periods.
2.1.8. Chroma Interpolation
A linear phase interpolator is used to convert the chroma
sampling rate from 10.125 MHz (4:2:2) to 20.25 MHz
(4:4:4). The frequency response of the interpolator is
shown in Fig. 2–6. All further processing is carried out at
the full sampling rate.
dB
MHz
0
–10
–20
–30
–40
–50
0
2
4
6
8
10
Fig. 2–6:
Frequency response of the chroma
interpolation filter
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