- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376602 > DDP3300A (MICRONAS SEMICONDUCTOR HOLDING AG) Single-Chip Display and Deflection Processor PDF資料下載
參數(shù)資料
| 型號： | DDP3300A |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 英文描述： | Single-Chip Display and Deflection Processor |
| 中文描述： | 單芯片顯示器和偏轉(zhuǎn)處理器 |
| 文件頁數(shù)： | 18/53頁 |
| 文件大?。?/td> | 1767K |
| 代理商： | DDP3300A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁當前第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁
DDP 3300 A
PRELIMINARY DATA SHEET
MICRONAS INTERMETALL
18
phase
comparator
&
lowpass
PLL2
composite
sync
generator
E/W
correction
sawtooth
PWM
15 bit
CSY
E/W
ouput
V
output
V
flyback
PWM
15 bit
DCO
front
sync
interface
FSY
VDATA
main
sync
generator
vertical
serial
data
phase
comparator
&
lowpass
PLL3
1:64
&
output
stage
H
flyback
H
drive
DCO
display
timing
line
counter
blanking, clamping, etc.
clock & control
sinewave
generator
&
DAC
LPF
Standby clock
Fig. 2–16:
Deflection processing block diagram
MSY
vertical reset
skew
measure–
ment
M1
M2
(not in scale)
M1
M2
F
V
l[0]
l[7]
line
[8]
not
Parity
input
analog
video
MSY
not
not
not
not
timing reference for PICTURE bus
– chroma multiplex sync
– active picture data after xxx clocks
V:
Vert. blanking
0 = off
1 = on
Field #
0 = Field 1
1 = Field 2
line: Field line #
1...N
F:
Parity
Fig. 2–17:
Main sync format
2.3.2. Horizontal Phase Adjustment
This section describes a simple way to align PLL phases
and the horizontal frame position.
1. The parameter NEWLIN in the VPC 320X has to be
adjusted. The minimum possible value is 34 (recom-
mended for a standard 4:3 signal).
2. With HDRV, the duration of the horizontal drive pulse
has to be adjusted.
3. With POFS2, the clamping pulse for the analog RGB
input has to be adjusted to the correct position, e.g.
the pedestal of the generator signal.
4. With POFS3, the horizontal position of the analog
RGB signal (from SCART) has to be adjusted.
5. With HPOS, the digital RGB output signal (from VPC)
has to be adjusted to the correct horizontal position.
6. With HBST and HBSO, the start and stop values for
the horizontal blanking have to be adjusted.
相關PDF資料 |
PDF描述 |
|---|---|
| DDP3310B | Display and Deflection Processor |
| DDR-TJS-T2 | LED AlInGaP |
| DD0-SJS-S1 | LED AlInGaP |
| DD0-SJS-S2 | LED AlInGaP |
| DD0-SJS-T1 | LED AlInGaP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DDP3300A(DIP64) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Consumer IC |
| DDP3300A(PLCC68) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TV/Video Signal Processor |
| DDP3300A(SDIP64) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TV/Video Signal Processor |
| DDP3300AD3 | 制造商:MICRONAS 功能描述:New |
| DDP3300APSD3 | 制造商:MICRONAS 功能描述:New |
發(fā)布緊急采購，3分鐘左右您將得到回復。