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參數(shù)資料
| 型號： | DDP3300A |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 英文描述： | Single-Chip Display and Deflection Processor |
| 中文描述： | 單芯片顯示器和偏轉(zhuǎn)處理器 |
| 文件頁數(shù)： | 17/53頁 |
| 文件大?。?/td> | 1767K |
| 代理商： | DDP3300A |
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DDP 3300 A
PRELIMINARY DATA SHEET
MICRONAS INTERMETALL
17
2.3. Synchronization and Deflection
The synchronization and deflection processing is
distributed over front-end, e.g., the VPC 320X and the
DDP 3300 A back end. The video clamping, horizontal
and vertical sync separation and all video related timing
information are processed in the front end. Most of the
processing that runs at the horizontal frequency is pro-
grammed on the internal Fast Processor (FP). Also the
values for vertical & East/West deflection are calculated
by the FP software.
The information extracted by the video sync processing
is multiplexed onto the hardware front sync signal (FSY)
and distributed to the rest of the video processing sys-
tem. The format of the front sync signal is given in
Fig. 2–15.
The data for the vertical deflection, the sawtooth and the
East/West correction signal is calculated in the
VPC 320X. The data is transferred to the back-end by a
single wire interface.
The display related synchronization, i.e. generation of
horizontal and vertical drive and synchronization of hori-
zontal and vertical drive to the video timing extracted in
the front-end, are implemented in hardware in the back-
end.
F1
(not in scale)
input
analog
video
FSY
F1
Parity
V:
Vert. Sync
0 = off
1 = on
F:
Field #
0 = field 1
1 = field 2
H:
Helper
Fig. 2–15:
Front sync format
F0
skew
MSB
skew
LSB
F
V
F0: reserved
H
2.3.1. Deflection Processing
The deflection processing generates the signals for the
horizontal and vertical drive (see Fig. 2–16). This block
contains two phase-locked loops:
– PLL2 generates the horizontal and vertical timing, e.g.
blanking, clamping and composite sync. Phase and
frequency are synchronized by the front sync signal.
– PLL3 adjusts the phase of the horizontal drive pulse
and compensates for the delay of the horizontal output
stage. Phase and frequency are synchronized by the
oscillator signal of PLL2.
The horizontal drive circuitry uses a digital sine wave
generator to produce the exact (subclock) timing for the
drive pulse. The generator runs at 1 MHz; in the output
stage the frequency is divided down to give drive-pulse
period and width. In standby mode, the output stage is
driven from an internal 1 MHz clock that is derived from
the 5 MHz clock input signal and a fixed drive pulse width
is used. When the circuit is switched out of standby
operation the drive pulse width is programmable. The
horizontal drive uses a high voltage (8V) open drain out-
put transistor.
The Main Sync (MSY) signal that is generated from
PLL3 is a multiplex of all display-related data
(Fig. 2–17). This signal is intended for use by other pro-
cessors, e.g. a PIP processor can use this signal to ad-
just to a certain display position.
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