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參數(shù)資料
| 型號： | DDP3300A |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 英文描述： | Single-Chip Display and Deflection Processor |
| 中文描述： | 單芯片顯示器和偏轉(zhuǎn)處理器 |
| 文件頁數(shù)： | 21/53頁 |
| 文件大小： | 1767K |
| 代理商： | DDP3300A |
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PRELIMINARY DATA SHEET
DDP 3300 A
MICRONAS INTERMETALL
21
locked clock from the horizontal PLL is performed by the
CCU.
VSTBY
VSUPD
～
50
μ
s
normal
mode
standby
mode
Internal
Reset
internal
oszillator
CLK5
5 MHz Clock
Clock
Release
HOUT
Fig. 2–20:
DDP power on, standby on/off
～
4
μ
s
normal
mode
2.4.3. DDP Standby On/Off
Switching the DDP to Standby Mode is more critical be-
cause of the HOUT output signal. Before the standby
mode is entered, the clock source for the horizontal out-
put generator has to be switched to the standby clock.
Switching to Standby Mode can be done by the CCU as
a reaction to a remote control command (see register 53,
EHPLL
disable) or by the internal voltage supervision
of the DDP. This voltage supervision activates the Power
Down signal when the supply for the digital circuits
(VSUPD) goes below V
SUPD–pd
(
Down signal switches the clock source for the HOUT
generation to the standby clock and sets the duty factor
to 50%. This is exactly what the EHPLL bit does.
4.5 V). The Power
Because the clocks from the DDP–pll and the standby
clock are not in phase, the actual phase (High/Low) of
the HOUT signal may be up to one pll or standby clock
(
1
μ
s) longer than a regular one when the clock source
is changed.
The voltage supervising reacts if VSUPD goes below
V
SUPD–pd
for more than 50 ns. This Power Down signal
is extended by 50
μ
s after VSUPD is back again.
When switched off, the negative slope of the supply
voltage VSUPD should not be larger than approximately
0.2 V/
μ
s (see Recommended Operating Conditions).
RESETQ
POR
UPDATE
4
μ
s
60
μ
s
Fig. 2–21:
External RESET
2.4.4. Reset DDP
Reset of most functions (exception see below) is per-
formed by different sources:
– power on circuit (VSTBY, VSUPD)
– reset pin (DDP)
voltage
superv.
5 MHz clock
release clock
(to HOUT gen)
VSTBY
Reset Pin
R
voltage
superv.
VSUPD
Reset
CLK5
CLK5
observer
Fig. 2–22:
DDP reset generation
If one of these sources creates a reset, all the internal
registers and counters are set to zero. When this reset
source becomes inactive, the internal reset is still active
for 4
μ
s. After that time all the internal registers are
loaded with the values defined in the defaults ROM. All
the registers which are updated with the vertical sync
(chain registers) get these values with the next vertical
sync. During this initialization procedure (approx. 60
μ
s)
it is not possible to access the DDP via the I
2
C-bus.
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