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參數(shù)資料
| 型號： | DDP3300A |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 英文描述： | Single-Chip Display and Deflection Processor |
| 中文描述： | 單芯片顯示器和偏轉(zhuǎn)處理器 |
| 文件頁數(shù)： | 32/53頁 |
| 文件大?。?/td> | 1767K |
| 代理商： | DDP3300A |
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DDP 3300 A
PRELIMINARY DATA SHEET
MICRONAS INTERMETALL
32
Short Description
Type
Pin Name
Connection
(if not used)
Pin No.
PSDIP
64-pin
PLCC
68-pin
60
40
GNDD
Y5
IN
Picture Bus Luma
61
39
GNDD
NC
Not connected
62
38
GNDD
Y6
IN
Picture Bus Luma
63
37
GNDD
Y7
IN
Picture Bus Luma (LSB)
64
36
GNDD
NC
Not connected
65
–
X
GNDD
Ground, Digital Circuitry
66
35
GNDD
NC
Not connected
67
34
X
VSUPP
Supply Voltage, Output Pin Driver
68
33
LV
CSY
OUT
Composite Sync Output
4.3. Pin Descriptions (Pin Numbers for PLCC68)
NC = not connected
Pin 1 – Main Sync Signal Output
MSY
(Fig. 4–5)
This pin supplies the front end ICs with the main horizon-
tal sync information, locked to the horizontal flyback.
Also line number, field even/odd and vertical blanking in-
formation is included.
Pin 3 – Front Sync Signal Input
FSY
(Fig. 4–11)
This pin gets the front horizontal sync information from
the video decoder VPC 32XX. Also skew, vertical sync,
field even/odd and PAL-plus helper line indication is in-
cluded.
Pin 4 – 5 MHz Clock Input
CLK5
(Fig. 4–7)
5 MHz clock required for HOUT and CSY generation
during standby mode.
Pin 5 – Horizontal Drive
HOUT
(Fig. 4–13)
This open drain output supplies the drive pulse for the
horizontal output stage. The gating with the flyback
pulse is selectable by software.
Pin 6 – Standby Supply Voltage
VSTDBY
In standby mode this pin supplies the horizontal drive cir-
cuitry.
Pin 7 – Horizontal Flyback Input
HFLB
(Fig. 4–9)
Via this pin the horizontal flyback pulse is supplied to the
DDP.
Pin 8 – Vertical Protection Input
VPROT
(Fig. 4–9)
The vertical protection circuitry prevents the picture tube
from burn-in in the event of a malfunction of the vertical
deflection stage. During vertical blanking, a signal level
of 2.5V is sensed. If a negative edge cannot be detected,
the RGB output signals are blanked.
Pin 9 – Safety Input,
SAFETY
(Fig. 4–9)
This is a three-level input. Low level means normal func-
tion. At the medium level RGB signals are blanked and
at high level RGB signals are blanked and horizontal
drive is shut off.
Pin 10 – I
2
C Clock Input
SCL
(Fig. 4–10)
Via this pin the clock signal for the I
2
C-bus is supplied.
Pin 11 – I
2
C Data Input/Output
SDA
(Fig. 4–10)
Via this pin the I
2
C-bus data are written to or read from
the DDP.
Pin 12 – Test Input
TEST
(Fig. 4–7)
This pin enables factory test modes. For normal opera-
tion it must be connected to ground.
Pin 13 – Reset Input
RES
(Fig. 4–7)
A low level on this pin resets the DDP.
Pin 14,15 – Range Switch for Meas. ADC
RSW1
RSW2
(Fig. 4–14 )
These pins are open drain pulldown outputs. During cut-
off measurement both switches are off. During white
drive measurement RSW1 is switched off and RSW2 is
switched on. During the rest of time both switches are
on.
Pin 16 – Measurement ADC Input
SENSE
(Fig. 4–9)
This is the input of the analog to digital converter for the
picture and tube measurement. Three ranges of mea-
surement are selectable with RSW1 and RSW2.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DDP3300A(DIP64) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Consumer IC |
| DDP3300A(PLCC68) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TV/Video Signal Processor |
| DDP3300A(SDIP64) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TV/Video Signal Processor |
| DDP3300AD3 | 制造商:MICRONAS 功能描述:New |
| DDP3300APSD3 | 制造商:MICRONAS 功能描述:New |
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