參數(shù)資料
型號： DDP3300A
廠商： MICRONAS SEMICONDUCTOR HOLDING AG
英文描述： Single-Chip Display and Deflection Processor
中文描述： 單芯片顯示器和偏轉(zhuǎn)處理器
文件頁數(shù)： 25/53頁
文件大?。?/td> 1767K
代理商： DDP3300A
DDP 3300 A
PRELIMINARY DATA SHEET
MICRONAS INTERMETALL
25
Name
Default
Function
Mode
Number
of bits
I
2
C sub
address
4c
9
w v
digital OSD insertion contrast for R (amplitude range: 0 to 255)
bit [3:0]
0..13
R amplitude = CLUTn · (DRCT + 4)
14,15
invalid
picture frame insertion contrast for R (ampl. range: 0 to 255)
bit [7:4]
0..13
R amplitude = PFCR · (PFRCT + 4)
14,15
invalid
8
8
DRCT
PFRCT
48
9
w v
digital OSD insertion contrast for G (amplitude range: 0 to 255)
bit [3:0]
0..13
G amplitude = CLUTn · (DGCT + 4)
14,15
invalid
picture frame insertion contrast for G (ampl. range: 0 to 255)
bit [7:4]
0..13
G amplitude = PFCG · (PFGCT + 4)
14,15
invalid
8
8
DGCT
PFGCT
44
9
w v
digital OSD insertion contrast for B (amplitude range: 0 to 255)
bit [3:0]
0..13
B amplitude = CLUTn · (DBCT + 4)
14,15
invalid
picture frame insertion contrast for B (ampl. range: 0 to 255)
bit [7:4]
0..13
B amplitude = PFCB · (PFBCT + 4)
14,15
invalid
8
8
DBCT
PFBCT
PICTURE FRAME GENERATOR
4F
9
w v
bit [8:0] horizontal picture frame begin
code 0 = picture frame generator horizontally disabled
code 1FF = full frame
0
PFGHB
53
9
w v
bit [8:0] horizontal picture frame end
0
PFGHE
63
9
w v
bit [8:0] vertical picture frame begin
code 0 = picture frame generator vertically disabled
270
PFGVB
6f
9
w v
bit [8:0] vertical picture frame end
56
PFGVE
enable and priority – see under ‘PRIORITY BUS’
picture frame color – see under ‘COLOR LOOK-UP TABLE’
SCAN VELOCITY MODULATION
62
9
w v
video mode coefficients
bit [5:0]
gain1
bit [8:6]
differentiator delay 1 (0= filter off, 1...6= delay)
60
4
SVG1
SVD1
5e
9
w v
text mode coefficients
bit [5:0]
bit [8:6]
gain 2
differentiator delay 2 (0= filter off, 1...6= delay)
60
4
SVG2
SVD2
5a
9
w v
limiter
bit [6:0]
bit [8:5]
limit value
not used, set to ”0”
100
0
SVLIM
56
9
w v
delay and coring
bit [3:0]
adjustable delay, in 1/2 display clock steps,
(value 5 : delay of SVMOUT is the same as for
RGBOUT
coring value
not used, set to ”0”
bit [7:4]
bit [8]
7
0
SVDEL
SVCOR
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