- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376602 > DDP3300A (MICRONAS SEMICONDUCTOR HOLDING AG) Single-Chip Display and Deflection Processor PDF資料下載
參數(shù)資料
| 型號： | DDP3300A |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 英文描述： | Single-Chip Display and Deflection Processor |
| 中文描述： | 單芯片顯示器和偏轉(zhuǎn)處理器 |
| 文件頁數(shù)： | 5/53頁 |
| 文件大?。?/td> | 1767K |
| 代理商： | DDP3300A |
第1頁第2頁第3頁第4頁當(dāng)前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁
PRELIMINARY DATA SHEET
DDP 3300 A
MICRONAS INTERMETALL
5
1.2. DDP Applications
Fig. 1–2 depicts several DDP applications. Since the
DDP functions as a video back-end, it must be
complemented with additional functionality to form a
complete TV set.
The DDP 3310 B will be a further development of the
DDP 3300 A. It is targeted for a system with a horizontal
frequency of 32 kHz and a vertical frequency of 100 or
120 Hz.
The VPC3210A/3211B processes all worldwide analog
video signals (including the European PALplus) and al-
lows nonlinear Panorama aspect ratio conversion. Thus
4:3 and 16:9 systems can easily be configured by soft-
ware. The aspect ratio scaling is also used as a sample
rate converter to provide a line-locked digital component
output bus (YCrCb) compliant to ITUR–601. All video
processing and line-locked clock/data generation is
derived from a single 20.25 MHz crystal. An optional
adaptive 2-line combfilter (VPC3211B) performs Y/C
separation for PAL and NTSC and all of their substan-
dards. Both versions of the VPC are plug-in compatible.
The CIP 3250 A provides a high-quality analog RGB in-
terface with character insertion capability. This allows
appropriate processing of external sources such as
MPEG2 set-top boxes in transparent (4:2:2) quality. Fur-
thermore, it translates RGB/Fastblank signals to the
common digital video bus and makes those signals
available for 100 Hz processing. In some European
countries (Italy), this feature is mandatory.
The IP indicates memory based image processing, such
as scan rate conversion, vertical processing (Zoom), or
PAL+ reconstruction.
Examples:
– Europe: 15 kHz/50 Hz
→
32 kHz/100 Hz interlaced
– US: 15 kHz/60 Hz
→
31 kHz/60 Hz non-interlaced
Note that the VPC supports memory based applications
through line-locked clocks, syncs, and data. CIP may
run either with the native DIGIT3000 clock but also with
a line-locked clock system.
RGB
CVBS
CIP
3250A
H/V
Defl.
IP
RGB
DDP
3300A
CVBS
VPC
320X
H/V
Defl.
C
1
S
PAL+
100 Hz
RGB
RGB
R
F
I
Fig. 1–2:
DDP 3300 A Applications
VPC
321X
DDP
3310B
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DDP3310B | Display and Deflection Processor |
| DDR-TJS-T2 | LED AlInGaP |
| DD0-SJS-S1 | LED AlInGaP |
| DD0-SJS-S2 | LED AlInGaP |
| DD0-SJS-T1 | LED AlInGaP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DDP3300A(DIP64) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Consumer IC |
| DDP3300A(PLCC68) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TV/Video Signal Processor |
| DDP3300A(SDIP64) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TV/Video Signal Processor |
| DDP3300AD3 | 制造商:MICRONAS 功能描述:New |
| DDP3300APSD3 | 制造商:MICRONAS 功能描述:New |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。