參數(shù)資料
型號: DAC1627D1G25
廠商: NXP SEMICONDUCTORS
元件分類: DAC
中文描述: PARALLEL, WORD INPUT LOADING, 0.02 us SETTLING TIME, 16-BIT DAC, PQCC72
封裝: 10 X 10 MM, 0.85 MM HEIGHT, PLASTIC, SOT813-3, HVQFN-72
文件頁數(shù): 8/69頁
文件大?。?/td> 1677K
代理商: DAC1627D1G25
DAC1627D1G25
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1 — 29 April 2011
8 of 69
NXP Semiconductors
DAC1627D1G25
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
9. Characteristics
Table 5.
V
DDA(1V8)
= 1.8 V; V
DDD(1V8)
= 1.8 V; V
DDA(3V3)
= 3.3 V; Typical values measured at T
amb
= +25
°
C; R
L
= 50
Ω
; I
O(fs)
= 20 mA;
maximum sample rate used; external PLL; no auxiliary DAC; no inverse sinus x/x; no output correction; output load condition
defined in
Figure 22
; output level = 1 V (p-p).
Symbol
Parameter
Conditions
Characteristics
Test
[1]
Min
Typ
Max
Unit
V
DDA(3V3)
analog supply
voltage (3.3 V)
digital supply
voltage (1.8 V)
analog supply
voltage (1.8 V)
analog supply
current (3.3 V)
digital supply
current (1.8 V)
C
3.15
3.3
3.45
V
V
DDD(1V8)
C
1.7
1.8
1.9
V
V
DDA(1V8)
C
[2]
1.7
1.8
1.9
V
I
DDA(3V3)
Aux DAC on
C
<tbd>
63
<tbd>
mA
I
DDD(1V8)
f
s
= 983.04 67;
×
4 interpolation; no NCO;
MDS on
f
s
= 620 Msps;
×
2 interpolation; NCO on;
no MDS
f
s
= 983.04 Msps; 1 V (p-p)
f
s
= 620 Msps; 1 V (p-p)
f
s
= 1228.8 Msps;
×
4 interpolation; NCO on;
MDS off
f
s
= 983.04 Msps;
×
4 interpolation; 5-bit NCO;
MDS off
f
s
= 983.04 Msps;
×
4 interpolation; NCO off;
MDS off
f
s
= 737.28 Msps;
×
4 interpolation; 5-bit NCO;
MDS off
f
s
= 620 Msps;
×
2 interpolation; 40-bit NCO;
MDS off
full power-down
C
<tbd>
520
<tbd>
mA
C
<tbd>
440
<tbd>
mA
I
DDA(1V8)
analog supply
current (1.8 V)
C
C
C
[2]
<tbd>
<tbd>
-
210
210
1770
<tbd>
<tbd>
-
mA
mA
mW
P
tot
total power
dissipation
C
-
1530
-
mW
C
-
<tbd>
-
mW
C
-
1540
-
mW
-
1400
-
mW
C
-
1.2
-
mW
Clock inputs (pins CLKP, CLKN)
V
i(clk)dif
differential clock
input voltage
R
i
input resistance
C
i
input capacitance
Digital inputs (pins LD[15]P to LD[0]P, LD[15]N to LD[0]N, LCKP and LCKN)
V
i
input voltage
|
V
gpd
|
< 50 mV
[3]
V
idth
input differential
threshold voltage
peak-to-peak
C
200
-
2000
mV
D
D
-
-
<tbd>
<tbd>
-
-
M
Ω
pF
C
C
825
100
-
-
1575
+100
mV
mV
|
V
gpd
|
< 50 mV
[3]
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