參數(shù)資料
型號: DAC1627D1G25
廠商: NXP SEMICONDUCTORS
元件分類: DAC
中文描述: PARALLEL, WORD INPUT LOADING, 0.02 us SETTLING TIME, 16-BIT DAC, PQCC72
封裝: 10 X 10 MM, 0.85 MM HEIGHT, PLASTIC, SOT813-3, HVQFN-72
文件頁數(shù): 16/69頁
文件大?。?/td> 1677K
代理商: DAC1627D1G25
DAC1627D1G25
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1 — 29 April 2011
16 of 69
NXP Semiconductors
DAC1627D1G25
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
10.4.2
Input port mapping
Inverting the order of the LSB and the MSB of the LVDS bus using bit WORD_SWAP in
register LD_CNTRL (see
Table 88
) also simplifies the design of the PCB (see
Table 9
).
Table 9.
Internal LVDS bus
10.4.3
Input port swapping
The LVDS DDR receiver block internally maps the incoming LVDS data bus into two
buses with a single data rate (
Figure 7
).
These two buses can be swapped internally using bit LDAB_SWAP of register
LD_CNTRL (see
Table 88
and
Figure 8
).
Input LVDS bus swapping
External LVDS bus
(WORD_SWAP = 0)
LD[15]P,N
LD[14]P,N
LD[13]P,N
LD[12]P,N
LD[11]P,N
LD[10]P,N
LD[9]P,N
LD[8]P,N
LD[7]P,N
LD[6]P,N
LD[5]P,N
LD[4]P,N
LD[3]P,N
LD[2]P,N
External LVDS bus
(WORD_SWAP = 1)
LD[0]P,N
LD[1]P,N
LD[2]P,N
LD[3]P,N
LD[4]P,N
LD[5]P,N
LD[6]P,N
LD[7]P,N
LD[8]P,N
LD[9]P,N
LD[10]P,N
LD[11]P,N
LD[12]P,N
LD[13]P,N
LDI[15]P,N
LDI[14]P,N
LDI[13]P,N
LDI[12]P,N
LDI[11]P,N
LDI[10]P,N
LDI[9]P,N
LDI[8]P,N
LDI[7]P,N
LDI[6]P,N
LDI[5]P,N
LDI[4]P,N
LDI[3]P,N
LDI[2]P,N
LDI[1]P,N
LDI[0]P,N
LD[1]P,N
LD[0]P,N
LD[14]P,N
LD[15]P,N
Fig 7.
LVDS DDR receiver mapping LDAB SWAP = 0
001aan393
A0
B0
A1
B1
A2
B2
A3
B3
LVDS
RECEIVER
LD[15..0]P/N
LCLKP/N
PA[15..0]
PB[15..0]
LCLK
A0
A1
to DAC A
to DAC B
A2
A3
B0
B1
B2
B3
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