參數(shù)資料
型號: DAC1627D1G25
廠商: NXP SEMICONDUCTORS
元件分類: DAC
中文描述: PARALLEL, WORD INPUT LOADING, 0.02 us SETTLING TIME, 16-BIT DAC, PQCC72
封裝: 10 X 10 MM, 0.85 MM HEIGHT, PLASTIC, SOT813-3, HVQFN-72
文件頁數(shù): 52/69頁
文件大?。?/td> 1677K
代理商: DAC1627D1G25
DAC1627D1G25
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1 — 29 April 2011
52 of 69
NXP Semiconductors
DAC1627D1G25
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Table 75.
BIAS[3:0]
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 72.
Default values are shown highlighted.
Bit
Symbol
3 to 0
DAC_CK_BIAS[3:0]
DAC_CURRENT_4 register (address 13h) bit description
Access
R/W
Value
-
Description
bias current control (see
Table 75
)
Table 73.
Default values are shown highlighted.
Bit
Symbol
3 to 0
DAC_CAS_BIAS[3:0]
DAC_CURRENT_5 register (address 14h) bit description
Access
R/W
Value
-
Description
bias current control (see
Table 75
)
Table 74.
Default values are shown highlighted.
Bit
Symbol
3 to 0
DAC_BLD_BIAS[3:0]
DAC_CURRENT_6 register (address 15h) bit description
Access
R/W
Value
-
Description
bias current control (see
Table 75
)
Bias current control table
Deviation from nominal current
30 %
20 %
10 %
0 %
+10 %
+20 %
+30 %
+40 %
Table 76.
Default values are shown highlighted.
Bit
Symbol
7
DAC_B_PON
DAC_PON_SLEEP register (address 16h) bit description
Access
R/W
Value
-
0
1
Description
DAC B power control
power-down
power on
DAC B mode selection
normal operation
Sleep mode
commutator B control
disable (power-down)
enable
DAC B bleed current control
disable (power-down)
enable
DAC A power control
power-down
power on
6
DAC_B_SLEEP
R
0
1
5
DAC_B_COM_PD
R
0
1
4
DAC_B_BLEED_PD
R
0
1
3
DAC_A_PON
R
0
1
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