參數(shù)資料
型號(hào): DAC1627D1G25
廠商: NXP SEMICONDUCTORS
元件分類: DAC
中文描述: PARALLEL, WORD INPUT LOADING, 0.02 us SETTLING TIME, 16-BIT DAC, PQCC72
封裝: 10 X 10 MM, 0.85 MM HEIGHT, PLASTIC, SOT813-3, HVQFN-72
文件頁(yè)數(shù): 43/69頁(yè)
文件大?。?/td> 1677K
代理商: DAC1627D1G25
DAC1627D1G25
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1 — 29 April 2011
43 of 69
NXP Semiconductors
DAC1627D1G25
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Table 35.
Default values are shown highlighted.
Bit
Symbol
3 to 0
DAC_A_DGAIN[11:8]
Register DAC_A_DGAIN_MSB (address 0Ch)
Access
R/W
Value
Description
DAC A digital gain control
most significant 4 bits for the DAC A digital gain
-
Table 36.
Default values are shown highlighted.
Bit
Symbol
7 to 0
DAC_B_DGAIN[7:0]
Register DAC_B_DGAIN_LSB (address 0Dh)
Access
R/W
Value
Description
DAC B digital gain control
least significant 8 bits for the DAC B digital gain
-
Table 37.
Default values are shown highlighted.
Bit
Symbol
3 to 0
DAC_B_DGAIN[11:8]
Register DAC_B_DGAIN_MSB (address 0Eh)
Access
R/W
Value
Description
DAC B digital gain control
most significant 4 bits for the DAC B digital gain
-
Table 38.
Default values are shown highlighted.
Bit
Symbol
3
A_DGAIN_E
Register DAC_OUT_CTRL (address 0Fh)
Access
R/W
Value
Description
DAC A digital gain control
disable
enable
DAC B digital gain control
disable
enable
DAC attenuation control
unity gain
3 dB gain
Digital DAC output clipping control
disable
enable
0
1
2
B_DGAIN_E
R/W
0
1
1
MINUS_3DB
R/W
0
1
0
CLIPPING_ENA
R/W
0
1
Table 39.
Default values are shown highlighted.
Bit
Symbol
7 to 0
CLIPPING_LEVEL[7:0]
Register DAC_CLIPPING (address 10h)
Access
R/W
Value
-
Description
Digital DAC output clipping level value
Table 40.
Default values are shown highlighted.
Bit
Symbol
7 to 0
DAC_A_OFFSET[7:0]
Register DAC_A_OFFSET_LSB (address 11h)
Access
R/W
Value
Description
DAC A digital offset value
least significant 8 bits for the DAC A digital offset
-
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