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| 型號： | DAC1627D1G25 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | DAC |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 0.02 us SETTLING TIME, 16-BIT DAC, PQCC72 |
| 封裝： | 10 X 10 MM, 0.85 MM HEIGHT, PLASTIC, SOT813-3, HVQFN-72 |
| 文件頁數(shù)： | 15/69頁 |
| 文件大?。?/td> | 1677K |
| 代理商： | DAC1627D1G25 |
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DAC1627D1G25
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1 — 29 April 2011
15 of 69
NXP Semiconductors
DAC1627D1G25
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
3. When the DAC clock and LVDS clock are stable, the SPI configuration is sent to the
DAC1627D1G25. Writing 0 in bits RST_DCLK and RST_LCLK of the register
MAIN_CNTRL (see
Table 80
) starts the automatic calibration. 30
μ
s after this
calibration, the DAC1627D1G25 is operational.
10.4 LVDS Data Input Format (DIF) block
The Data Input Formatting (DIF) block captures and resynchronizes data on the LVDS bus
with its own LCLKP/LCLKN clock. Each LVDS input buffer has an internal resistance of
100
Ω
, so an external resistor is not required. The DIF block includes two sub-blocks:
LDVS receiver:
Provides high flexibility for the LVDS interface, especially for the PCB layout and the
control of the input port polarity and the input port mapping.
Data format block:
Enables the adaptation, which ensures the support of several data encoding modes.
10.4.1
Input port polarity
The polarity of each individual LVDS input (LD[15]P to LD[0]P and LD[15]N to LD[0]N) can
be changed, ensuring a much easier PCB layout design. The input polarity is controlled
with bits LD_POL[7:0] in register LD_POL_LSB (see
Table 86
) and bits LD_POL[15:8] in
register LD_POL_MSB (see
Table 87
).
Fig 5.
Power-on sequence
001aan810
SPI bus
WRITE DAC CONFIGURATION
START CLOCK CALIBRATION
time
RESET_N
t
on
power in
specification
range
t
spi_start
t
rst
power supplies
Fig 6.
LVDS Data Input Format (DIF) block diagram
16
16
001aan392
LVDS
RECEIVER
to DAC A
to DAC B
PA[15..0]
PB[15..0]
16
16
I[15..0]
Q[15..0]
LCLK
LD[15]P
LD[15]N
LD[0]P
LD[0]N
LCLKP
LCLKN
DATA
FORMAT
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DAC1627D1G25/DB,598 | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 DAC DEMOBOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| DAC1627D1G25HN/C1, | 功能描述:調(diào)節(jié)器/解調(diào)器 DUAL 16b 1.25GSPS to 1.25 Gsps RoHS:否 制造商:Texas Instruments 封裝 / 箱體:PVQFN-N24 封裝:Reel |
| DAC1627D1G25HN/C1,551 | 功能描述:調(diào)節(jié)器/解調(diào)器 Dual 16-bit DAC, up to 1.25 Gsps RoHS:否 制造商:Texas Instruments 封裝 / 箱體:PVQFN-N24 封裝:Reel |
| DAC1627D1G25HN-C1 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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