參數(shù)資料
型號: DAC1627D1G25
廠商: NXP SEMICONDUCTORS
元件分類: DAC
中文描述: PARALLEL, WORD INPUT LOADING, 0.02 us SETTLING TIME, 16-BIT DAC, PQCC72
封裝: 10 X 10 MM, 0.85 MM HEIGHT, PLASTIC, SOT813-3, HVQFN-72
文件頁數(shù): 51/69頁
文件大?。?/td> 1677K
代理商: DAC1627D1G25
DAC1627D1G25
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1 — 29 April 2011
51 of 69
NXP Semiconductors
DAC1627D1G25
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
4 to 3
MDS_EN_PHASE[1:0]
R
MDS enable phase
enable phase = 0
enable phase = 1 (only for
×
2)
enable phase = 2 (only for
×
2 and
×
4)
enable phase = 3 (only for
×
2)
MDS-PRERUN phase active flag
false
true
MDS_LOCKOUT detected flag
false
true
MDS_LOCK flag
false
true
00
01
10
11
2
MDS_PRERUN
R
0
1
1
MDS_LOCKOUT
R
0
1
0
MDS_LOCK
R
0
1
Table 66.
Default values are shown highlighted.
Bit
Symbol
MDS_STATUS1 register (address 0Ah) bit description
…continued
Access
Value
Description
Table 67.
Default values are shown highlighted.
Bit
Symbol
3 to 0
DAC_AUX_BIAS[3:0]
DAC_CURRENT_AUX register (address 0Eh) bit description
Access
R/W
Value
-
Description
bias current control (see
Table 75
)
Table 68.
Default values are shown highlighted.
Bit
Symbol
3 to 0
DAC_DIG_BIAS[3:0]
DAC_CURRENT_0 register (address 0Fh) bit description
Access
R/W
Value
-
Description
bias current control (see
Table 75
)
Table 69.
Default values are shown highlighted.
Bit
Symbol
3 to 0
DAC_MST_BIAS[3:0]
DAC_CURRENT_1 register (address 10h) bit description
Access
R/W
Value
-
Description
bias current control (see
Table 75
)
Table 70.
Default values are shown highlighted.
Bit
Symbol
3 to 0
DAC_DRV_BIAS[3:0]
DAC_CURRENT_2 register (address 11h) bit description
Access
R/W
Value
-
Description
bias current control (see
Table 75
)
Table 71.
Default values are shown highlighted.
Bit
Symbol
3 to 0
DAC_SLV_BIAS[3:0]
DAC_CURRENT_3 register (address 12h) bit description
Access
R/W
Value
-
Description
bias current control (see
Table 75
)
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