參數(shù)資料
型號(hào): DAC1627D1G25
廠商: NXP SEMICONDUCTORS
元件分類: DAC
中文描述: PARALLEL, WORD INPUT LOADING, 0.02 us SETTLING TIME, 16-BIT DAC, PQCC72
封裝: 10 X 10 MM, 0.85 MM HEIGHT, PLASTIC, SOT813-3, HVQFN-72
文件頁(yè)數(shù): 59/69頁(yè)
文件大?。?/td> 1677K
代理商: DAC1627D1G25
DAC1627D1G25
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1 — 29 April 2011
59 of 69
NXP Semiconductors
DAC1627D1G25
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Table 90.
Default values are shown highlighted.
Bit
Symbol
7 to 0
I_DC_LEVEL[7:0]
Register I_DC_LVL_LSB(address 0Ch)
Access
R/W
Value
Description
I_DC_LEVEL
least significant 8 bits for I_DC_LEVEL
-
Table 91.
Default values are shown highlighted.
Bit
Symbol
7 to 0
I_DC_LEVEL[15:8]
Register I_DC_LVL_MSB(address 0Dh)
Access
R/W
Value
Description
I_DC_LEVEL
most significant 8 bits for I_DC_LEVEL
-
Table 92.
Default values are shown highlighted.
Bit
Symbol
7 to 0
Q_DC_LEVEL[7:0]
Register Q_DC_LVL_LSB(address 0Eh)
Access
R/W
Value
Description
Q_DC_LEVEL
least significant 8 bits for Q_DC_LEVEL
-
Table 93.
Default values are shown highlighted.
Bit
Symbol
7 to 0
Q_DC_LEVEL[15:8]
Register Q_DC_LVL_MSB(address 0Fh)
Access
R/W
Value
Description
Q_DC_LEVEL
most significant 8 bits for Q_DC_LEVEL
-
Table 94.
Default values are shown highlighted.
Bit
Symbol
7
DAC
Register TYPE_ID (address 1Bh)
Access
R
Value
Description
calibration
uncalibrated device
calibrated device
LVDS input interface
dual DAC
internal digital signal processing
interpolation filter + SSBM
SSBM
interpolation filter
none
DAC bit resolution
16 bits
14 bits
12 bits
10 bits
0
1
01
0
6 to 5
4
3 to 2
FRONTEND
DUAL
DSP
R
R
R
11
10
01
00
1 to 0
BIT_RES
R
00
01
10
11
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