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參數(shù)資料
| 型號： | CYP15G04K100V1 |
| 英文描述： | Physical Layer Devices |
| 中文描述： | 物理層設(shè)備 |
| 文件頁數(shù)： | 8/78頁 |
| 文件大?。?/td> | 1555K |
| 代理商： | CYP15G04K100V1 |
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CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 8 of 78
Macrocell
Within each logic block there are 16 macrocells. Each
macrocell accepts a sum of up to 16 product terms from the
product term array. The sum of these 16 product terms can be
output in either registered or combinatorial mode.
Figure 5
displays the block diagram of the macrocell. The register can
be asynchronously preset or asynchronously reset at the mac-
rocell level with the separate preset and reset product terms.
Each of these product terms features programmable polarity.
This allows the registers to be preset or reset based on an
AND expression or an OR expression.
An XOR gate in the PSI macrocell allows for many different
types of equations to be realized. It can be used as a polarity
mux to implement the true or complement form of an equation
in the product term array or as a toggle to turn the D flip-flop
into a T flip-flop. The carry-chain input mux allows additional
flexibility for the implementation of different types of logic. The
macrocell can utilize the carry chain logic to implement adders,
subtractors, magnitude comparators, parity tree, or even ge-
neric XOR logic. The output of the macrocell is either regis-
tered or combinatorial.
Carry Chain Logic
The PSI macrocell features carry chain logic, which is used for
fast and efficient implementation of arithmetic operations. The
carry logic connects macrocells in up to 4 logic blocks for a
total of 64 macrocells. Effective data path operations are im-
plemented through the use of carry-in arithmetic, which drives
through the circuit quickly.
Figure 5
shows that the carry chain
logic within the macrocell consists of two product terms (CPT0
and CPT1) from the PTA and an input carry-in for carry logic.
The inputs to the carry chain mux are connected directly to the
product terms in the PTA. The output of the carry chain mux
generates the carry-out for the next macrocell in the logic block
as well as the local carry input that is connected to an input of
the XOR input mux. Carry-in and a configuration bit are inputs
to an AND gate. This AND gate provides a method of segment-
ing the carry chain in any macrocell in the logic block.
Macrocell Clocks
Clocking of the register is highly flexible. Four global synchro-
nous clocks (GCLK[3:0]) and a Product Term clock (PTCLK)
are available at each macrocell register. Furthermore, a clock
polarity mux within each macrocell allows the register to be
clocked on the rising or the falling edge (see macrocell dia-
gram in
Figure 5
).
PRESET/RESET Configurations
The macrocell register can be asynchronously preset and re-
set using the PRESET and RESET mux. Both signals are ac-
tive high and can be controlled by either of two Preset/Reset
product terms (PRC[1:0] in
Figure 5
) or GND. In situations
where the PRESET and RESET are active at the same time,
RESET takes priority over PRESET.
Figure 5. PSI Macrocell
D
Q
PSET
RES
GCLK[3:0]
PTCLK
FROM PTM
Up To 16 PTs
CPT0
CPT1
P
0
1
0
1
To PIM
C
Carry Out
(to macrocell n+1)
Carry In
(from macrocell n-1)
PRESET
Mux
Clock
Polarity
Mux
RESET
Mux
Clock Mux
Carry Chain
Mux
XOR Input
Mux
Output Mux
Q
C
3
3
2
3
C
C
C
C
C
C
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