參數(shù)資料
型號(hào)： CYP15G04K100V1
英文描述： Physical Layer Devices
中文描述： 物理層設(shè)備
文件頁數(shù)： 67/78頁
文件大?。?/td> 1555K
代理商： CYP15G04K100V1
CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 67 of 78
BISTLE
LVTTL Input,
asynchronous,
internal pull-up
Transmit and Receive BIST Latch Enable. Active HIGH. When BISTLE = HIGH, the
signals on the BOE[7:0] inputs directly control the transmit and receive BIST enables.
When BOE[x] input is LOW, the associated transmit or receive channel is configured to
generate or compare the BIST sequence. When the BOE[x] input is HIGH, the associ-
ated transmit or receive channel is configured for normal data transmission or reception.
When BISTLE returns LOW, the last values present on BOE[7:0] are captured in the
internal BIST Enable latch. The specific mapping of BOE[7:0] signals to transmit and
receive BIST enables is listed in
Table 16
.
When the latch is closed, if the device is reset (TRSTZ is sampled LOW), the latch is
reset to disable BIST on all transmit and receive channels.
Receive Channel Power-Control Latch Enable. Active HIGH. When RXLE = HIGH, the
signals on the BOE[7:0] inputs directly control the power enables for the receive PLLs
and analog logic. When the BOE[7:0] input is HIGH, the associated receive channel A
through receive channel D PLL and analog logic are active. When the BOE[7:0] input is
LOW, the associated receive channel A through receive channel D PLL and analog logic
are placed in a non-functional power saving mode. When RXLE returns LOW, the last
values present on BOE[7:0] are captured in the internal RX PLL Enable latch. The
specific mapping of BOE[7:0] signals to the associated receive channel enables is listed
in
Table 16
.
When the latch is closed, if the device is reset (TRSTZ is sampled LOW), the latch is
reset to enable all receive channels.
BIST, Serial Output, and Receive Channel Enables.
These inputs are passed to and through the output enable latch when OELE is HIGH,
and captured in this latch when OELE returns LOW.
These inputs are passed to and through the BIST enable latch when BISTLE is HIGH,
and captured in this latch when BISTLE returns LOW.
These inputs are passed to and through the Receive Channel enable latch when RXLE
is HIGH, and captured in this latch when RXLE returns LOW. The specific mapping of
BOE[7:0] signals to transmit output enables is listed in Table 15
Link Fault Indication output. Active LOW. LFI is the logical OR of four internal conditions:
1. Received serial data frequency outside expected range
2. Analog amplitude below expected levels
3. Transition density lower than expected
4. Receive Channel disabled
RXLE
LVTTL Input,
asynchronous,
internal pull-up
BOE[7:0]
LVTTL Input,
asynchronous,
internal pull-up
LFIA
LFIB
LFIC
LFID
LVTTL Output,
synchronous to the
selected RXCLKx
↑
output or
REFCLK
↑
[36]
input,
asynchronous to
receive channel
enable/disable
Bonding Control
BONDST[1:0]
Bidirectional Open
Drain,
internal pull-up
Bonding Status. These signals are only used when multiple devices are bonded togeth-
er. They communicate the status of the present internal bonding and Elasticity Buffer
management events to the slave devices. These outputs change with the same timing
as the receive output data buses, but are connected only to all the slave PSI transceiver
block devices.
When MASTER = LOW, these are output signals and present the Elasticity Buffer status
from the selected receive channel of the device configured as the master. Receive
master channel selection is performed using the RXCKB+ and RXCKD+ inputs. These
status outputs indicate one of four possible conditions, on a synchronous basis, to the
slave devices. These condition are:
00
—
Word Sync Sequence received
01
—
Add one K28.5 immediately following the next framing character received
10
—
Delete next framing character received
11
—
Normal data
These outputs are driven only when the device is configured as a master, all four chan-
nels are bonded together, and the receive parallel interface is clocked by REFCLK
↑
.
Frequency Agile PSI
Name
Function
Signal Description
相關(guān)PDF資料
PDF描述
CYP15G0101DXA-BBC Telecomm/Datacomm
CYP15G0403DXB Physical Layer Devices
CYP15G0101 Single-channel HOTLink Transceiver
CYP15G0101DXB Single-channel HOTLink Transceiver
CYP15G0101DXB-BBC Single-channel HOTLink Transceiver
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CYP7C1048AC 制造商:Cypress Semiconductor 功能描述:
CYPCY2305SXC1H 制造商:Cypress Semiconductor 功能描述:
CYPD1103-35FNXIT 功能描述:IC MCU 32BIT 32KB FLASH 35WLCSP 制造商:cypress semiconductor corp 系列:EZ-PD? CCG1 包裝:剪切帶（CT） 零件狀態(tài):停產(chǎn) 應(yīng)用:USB Type C 核心處理器:ARM? Cortex?-M0 程序存儲(chǔ)器類型:閃存（32 kB） 控制器系列:- RAM 容量:4K x 8 接口:I2C，SPI，UART/USART，USB I/O 數(shù):31 電壓 - 電源:1.71 V ~ 5.5 V 工作溫度:-40°C ~ 85°C（TA） 安裝類型:* 封裝/外殼:35-UFBGA，WLCSP 供應(yīng)商器件封裝:35-WLCSP（3.23x2.10） 標(biāo)準(zhǔn)包裝:1
CYPD1121-40LQXI 功能描述:IC MCU 32BIT 32KB FLASH 40QFN 制造商:cypress semiconductor corp 系列:EZ-PD? CCG1 包裝:托盤 零件狀態(tài):有效 應(yīng)用:USB Type C 核心處理器:ARM? Cortex?-M0 程序存儲(chǔ)器類型:閃存（32 kB） 控制器系列:- RAM 容量:4K x 8 接口:I2C，SPI，UART/USART，USB I/O 數(shù):34 電壓 - 電源:1.71 V ~ 5.5 V 工作溫度:-40°C ~ 85°C（TA） 安裝類型:* 封裝/外殼:40-UFQFN 裸露焊盤 供應(yīng)商器件封裝:40-QFN（6x6） 標(biāo)準(zhǔn)包裝:490
CYPD1132-16SXI 功能描述:IC MCU 32BIT 32KB FLASH 16SOIC 制造商:cypress semiconductor corp 系列:EZ-PD? CCG1 包裝:管件 零件狀態(tài):有效 應(yīng)用:USB Type C 核心處理器:ARM? Cortex?-M0 程序存儲(chǔ)器類型:閃存（32 kB） 控制器系列:- RAM 容量:4K x 8 接口:I2C，SPI，UART/USART，USB I/O 數(shù):11 電壓 - 電源:1.71 V ~ 5.5 V 工作溫度:-40°C ~ 85°C（TA） 安裝類型:* 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商器件封裝:16-SOIC 標(biāo)準(zhǔn)包裝:480
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*