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參數(shù)資料
| 型號(hào)： | CYP15G04K100V1 |
| 英文描述： | Physical Layer Devices |
| 中文描述： | 物理層設(shè)備 |
| 文件頁數(shù)： | 17/78頁 |
| 文件大?。?/td> | 1555K |
| 代理商： | CYP15G04K100V1 |
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CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 17 of 78
Serial Transceiver Operation
The PSI transceiver block is a highly configurable device de-
signed to support reliable transfer of large quantities of data,
using high-speed serial links, from one or multiple sources to
one or multiple destinations. This device supports four single-
byte or single-character channels that may be combined to
support transfer of wider buses.
Frequency Agile PSI Transmit Data Path
Operating Modes
The transmit path of the PSI transceiver block supports four
character-wide data paths. These data paths are used in mul-
tiple operating modes as controlled by the TXMODE[1:0] in-
puts.
Input Register
Within these operating modes, the bits in the Input Register for
each channel support different bit assignments, based on
whether the character is unencoded, encoded with two control
bits, or encoded with three control bits. These assignments are
shown in
Table 8
.
Each input register captures a minimum of eight data bits and
two control bits on each input clock cycle. When the encoder
is bypassed, the control bits are part of the pre-encoded 10-bit
character.
When the Encoder is enabled (TXMODE[1]
≠
L), the
TXCTx[1:0] bits are interpreted along with the associated
TXDx[7:0] character to generate the specific 10-bit transmis-
sion character.
Phase-Align Buffer
Data from the input registers is passed either to the encoder
or to the associated Phase-Align buffer. When the transmit
paths are operated synchronous to REFCLK
↑
(TXCKSEL = L
and TXRATE = LOW), the Phase-Align Buffers are bypassed
and data is passed directly to the encoder blocks to reduce
latency.
When an Input-Register clock with an uncontrolled phase re-
lationship to REFCLK is selected (TXCLSEL
=
H) or if data is
captured on both edges of REFCLK (TXRATE = HIGH), the
Phase-Align Buffers are enabled. These buffers are used to
absorb clock phase differences between the presently select-
ed input clock and the internal character clock.
Initialization of these phase-align buffers takes place when the
TXRST input is sampled LOW by TXCLKA
↑
. When TXRST is
returned HIGH, the present input clock phase relative to
REFCLK
↑
is set. TXRST is an asynchronous input, but is sam-
pled internally to synchronize it to the internal transmit path
state machines. TXRST must be sampled LOW by a minimum
of two consecutive TXCLKA
↑
clocks to ensure the reset oper-
ation is initiated correctly on all channels.
Once set, the TXCLKA is allowed to skew in time up to half a
character period in either direction relative to REFCLK
↑
; i.e.,
±
180
°
. This time shift allows the delay paths of the character
clocks (relative to REFLCK
↑
) to change due to operating volt-
age and temperature, while not affecting the design operation.
If the phase offset, between the initialized location of the input
clock and REFCLK
↑
, exceeds the skew-handling capabilities
of the Phase-Align Buffer, an error is reported on the associ-
ated TXPERx output. This output will indicate a continuous
error until the Phase-Align Buffer is reset. While the error re-
mains active, the transmitter for the associated channel will
output a continuous C0.7 character to indicate to the remote
receiver that an error condition is present in the link.
In specific transmit modes it is also possible to reset the
Phase-Align Buffers individually and with minimal disruption of
the serial data stream. When the transmit interface is config-
ured for generation of atomic Word Sync Sequences
(TXMODE[1] = M) and a Phase-Align Buffer error is present,
the transmission of a Word Sync Sequence will re-center the
buffer and clear the error condition.
NOTE
: One or more K28.5 characters may be added or lost
from the data stream during this reset operation. When
used with non-Cypress devices that require a complete 16-
character Word Sync Sequence for proper receive Elastic-
ity Buffer alignment, it is recommend that the sequence be
followed by a second Word Sync Sequence to ensure prop-
er operation.
Encoder
The character, received from the input register or phase-align
buffer is then passed to the Encoder logic. This block interprets
each character and any associated control bits, and outputs a
10-bit transmission character.
Depending on the configured operating mode, the generated
transmission character may be
the 10-bit pre-encoded character accepted in the input reg-
ister
the 10-bit equivalent of the 8-bit Data character accepted in
the input register
the 10-bit equivalent of the 8-bit Special Character code
accepted in the input register
the 10-bit equivalent of the C0.7 SVS character if a Phase-
Align Buffer overflow or underflow error is present
a character that is part of the 511-character BIST sequence
a K28.5 character generated as an individual character or
as part of the 16-character Word Sync Sequence.
The selection of the specific characters generated are con-
trolled by the TXMODE[1:0], TXCTx[1:0], and TXDx[7:0] in-
puts for each character.
Table 8. Input Register Bit Assignments
Signal Name
TXDx[0]
(LSB)
TXDx[1]
TXDx[2]
TXDx[3]
TXDx[4]
TXDx[5]
TXDx[6]
TXDx[7]
TXCTx[0]
TXCTx[1]
(MSB)
Unencoded
DINx[0]
DINx[1]
DINx[2]
DINx[3]
DINx[4]
DINx[5]
DINx[6]
DINx[7]
DINx[8]
DINx[9]
Encoded
2-bit
Control
TXDx[0]
TXDx[1]
TXDx[2]
TXDx[3]
TXDx[4]
TXDx[5]
TXDx[6]
TXDx[7]
TXCTx[0]
TXCTx[1]
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