參數(shù)資料
型號： CYP15G04K100V1
英文描述： Physical Layer Devices
中文描述： 物理層設(shè)備
文件頁數(shù)： 40/78頁
文件大?。?/td> 1555K
代理商： CYP15G04K100V1
CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 40 of 78
Channel Memory Timing Parameter Values
Description
200
Unit
Parameter
Dual-Port Asynchronous Mode Parameters
t
CHMAA
Channel memory access time. Delay from address change to read data out
t
CHMPWE
Write enable pulse width
t
CHMSA
Address set-up to the beginning of write enable
t
CHMHA
Address hold after the end of write enable with both signals from the same I/O block
t
CHMSD
Data set-up to the end of write enable
t
CHMHD
Data hold after the end of write enable
t
CHMBA
Channel memory asynchronous dual port address match (busy access time)
Dual-Port Synchronous Mode Parameters
Clock cycle time for flow through read and write operations (from macrocell register
through channel memory back to a macrocell register in the same cluster)
Clock cycle time for pipelined read and write operations (from channel memory
input register through the memory to channel memory output register)
t
CHMS
Address, data, and WE set-up time of pin inputs, relative to a global clock
t
CHMH
Address, data, and WE hold time of pin inputs, relative to a global clock
t
CHMDV1
Global clock to data valid on output pins for flow through data
t
CHMDV2
Global clock to data valid on output pins for pipelined data
t
CHMBDV
Channel memory synchronous dual-port address match (busy, clock to data valid)
t
CHMMACS1
Channel memory input clock to macrocell clock in the same cluster
t
CHMMACS2
Channel memory output clock to macrocell clock in the same cluster
t
MACCHMS1
Macrocell clock to channel memory input clock in the same cluster
t
MACCHMS2
Macrocell clock to channel memory output clock in the same cluster
Synchronous FIFO Data Parameters
t
CHMCLK
Read and write minimum clock cycle time
t
CHMFS
Data, read enable, and write enable set-up time relative to pin inputs
t
CHMFH
Data, read enable, and write enable hold time relative to pin inputs
Data access time to output pins from rising edge of read clock (read clock to data
valid)
t
CHMMACS
Channel memory FIFO read clock to macrocell clock for read data
t
MACCHMS
Macrocell clock to channel memory FIFO write clock for write data
t
CHMFO
Read or write clock to respective flag output at output pins
t
CHMMACF
Read or write clock to macrocell clock with FIFO flag
t
CHMFRS
Master Reset Pulse Width
t
CHMFRSR
Master Reset Recovery Time
t
CHMFRSF
Master Reset to Flag and Data Output Time
t
CHMSKEW1
Read/Write Clock Skew Time for Full Flag
t
CHMSKEW2
Read/Write Clock Skew Time for Empty Flag
t
CHMSKEW3
Read/Write Clock Skew Time for Boundary Flags
Internal Parameters
t
CHMCHAA
Asynchronous channel memory access time from input of channel memory to
output of channel memory
Min.
Max.
11
ns
ns
ns
ns
ns
ns
ns
6.0
2.0
1.0
6.0
0.5
9.0
t
CHMCYC1
10
ns
t
CHMCYC2
5.0
ns
3.3
0.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
7.5
9.0
9.0
5.0
5.0
7.0
5.0
4.0
0.0
7.0
ns
ns
ns
t
CHMFRDV
5.0
5.0
11
9
5.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.0
10.0
2.0
2.0
5.0
7.0
ns
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