參數(shù)資料
型號： CYP15G04K100V1
英文描述： Physical Layer Devices
中文描述： 物理層設(shè)備
文件頁數(shù)： 16/78頁
文件大?。?/td> 1555K
代理商： CYP15G04K100V1
CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 16 of 78
Timing Model
One important feature of the PSI family is the simplicity of its
timing. All combinatorial and registered/synchronous delays
are worst case and system performance is static (as shown in
the AC specs section) as long as data is routed through the
same horizontal and vertical channels.
Figure 12
illustrates the
true timing model for the 200-MHz devices.
For synchronous
clocking of macrocells, a delay is incurred from macrocell clock
to macrocell clock of separate Logic Blocks within the same
cluster, as well as separate Logic Blocks within different clus-
ters. This is shown as t
and t
in
Figure 12.
For combi-
natorial paths, any input to any output (from corner to corner
on the device), incurs a worst-case delay in the 100K gate PSI
regardless of the amount of logic or which horizontal and ver-
tical channels are used. This is the t
PD
shown in
Figure 12.
For
synchronous systems, the input set-up time to the output mac-
rocell register and the clock-to-output time are shown as the
parameters t
and t
shown in the
Figure 12.
These
measurements are for any output and synchronous clock, re-
gardless of the logic placement.
PSI features:
no dedicated vs. I/O pin delays
no penalty for using 0
–
16 product terms
no added delay for steering product terms
no added delay for sharing product terms
no output bypass delays
The simple timing model of the PSI family eliminates unexpect-
ed performance penalties.
Figure 12. Timing Model for 100K gate PSI Devices
Channel
RAM
4
GCLK[3:0]
LB 0
PIM
RAM
LB 5
LB 4
LB 6
LB 7
LB 2
LB 3
LB 1
RAM
Channel
RAM
4
LB 0
PIM
Cluster
RAM
LB 5
LB 4
LB 6
LB 7
LB 2
LB 3
LB 1
Cluster
RAM
Channel
RAM
4
LB 0
PIM
Cluster
RAM
LB 5
LB 4
LB 6
LB 7
LB 2
LB 3
LB 1
Cluster
RAM
Channel
RAM
4
LB 0
PIM
8 Kb
SRAM
LB 5
LB 4
LB 6
LB 7
LB 2
LB 3
LB 1
8 Kb
SRAM
Channel
RAM
4
GCLK[3:0]
LB 0
PIM
RAM
LB 5
LB 4
LB 6
LB 7
LB 2
LB 3
LB 1
RAM
4
LB 0
PIM
LB 5
LB 4
LB 6
LB 7
LB 2
LB 3
LB 1
Cluster
RAM
4
LB 0
PIM
Cluster
RAM
LB 5
LB 4
LB 6
LB 7
LB 2
LB 3
LB 1
RAM
Channel
RAM
4
LB 0
PIM
Cluster
RAM
LB 5
LB 4
LB 6
LB 7
LB 2
LB 3
LB 1
Cluster
RAM
Channel
RAM
4
GCLK[3:0]
LB 0
PIM
RAM
LB 5
LB 4
LB 6
LB 7
LB 2
LB 3
LB 1
RAM
Channel
RAM
4
LB 0
PIM
Cluster
RAM
LB 5
LB 4
LB 6
LB 7
LB 2
LB 3
LB 1
Cluster
RAM
Channel
RAM
4
LB 0
PIM
Cluster
RAM
LB 5
LB 4
LB 6
LB 7
LB 2
LB 3
LB 1
Cluster
RAM
Channel
RAM
4
LB 0
PIM
RAM
LB 5
LB 4
LB 6
LB 7
LB 2
LB 3
LB 1
Cluster
RAM
Channel
RAM
Channel
RAM
Cluster
Cluster
RAM
t
MCS
t
PD
t
SCS
t
MCCO
t
SCS2
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