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參數(shù)資料
| 型號： | CYP15G04K100V1 |
| 英文描述： | Physical Layer Devices |
| 中文描述： | 物理層設備 |
| 文件頁數(shù)： | 20/78頁 |
| 文件大?。?/td> | 1555K |
| 代理商： | CYP15G04K100V1 |
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CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 20 of 78
state of any of the other bits in the A or B input registers. In a
similar fashion, anytime TXCTD[0] is sampled HIGH, both the
C and D channels start generation of an Atomic Word Sync
Sequence.
When RXMODE[1] = H, the PSI transceiver block is configured
for quad-channel bonding, such that channels A, B, C, and D
are bonded together to form a four-character-wide path. When
operated in this mode, the TXCTA[0] and TXCTB[0] inputs
control the interpretation of the data on all four channels. The
characters generated on these bonded channels are con-
trolled by the associated TXCTx[1] bit. The specific characters
generated by these bits are listed in
Table 15
.
Unlike dual-channel modes, when all four channels are bond-
ed together, the TXCTC[0] and TXCTD[0] inputs are not inter-
preted.
Transmit BIST
The transmitter interfaces contain internal pattern generators
that can be used to validate both device and link operation.
These generators are enabled by the associated BOE[x] sig-
nals listed in
Table 16
(when the BISTLE latch enable input is
HIGH). When enabled, a register in the associated transmit
channel becomes a signature pattern generator by logically
converting to a Linear Feedback Shift Register (LFSR). This
LFSR generates a 511-character sequence that includes all
Data and Special Character codes, including the explicit viola-
tion symbols. This provides a predictable yet pseudo-random
sequence that can be matched to an identical LFSR in the
attached Receiver(s).
When the BISTLE signal is HIGH, any BOE[x] input that is
LOW enables the BIST generator in the associated transmit
channel (or the BIST checker in the associated receive chan-
nel). When BISTLE returns LOW, the values of all BOE[x] sig-
nals are captured in the BIST Enable Latch. These values re-
main in the BIST Enable Latch until BISTLE is returned high
to open the latch again. All captured signals in the BIST Enable
Latch are set HIGH (i.e., BIST is disabled) following a a device
reset (TRSTZ is sampled LOW).
All data and data-control information present at the associated
TXDx[7:0] and TXCTx[1:0] inputs are ignored when BIST is
active on that channel. If the receive channels are configured
for common clock operation (RXCKSEL
≠
MID) each pass is
preceded by a 16-character Word Sync Sequence to allow
Elasticity Buffer alignment and management of clock-frequen-
cy variations.
Table 14. TX Modes 5 and 8, Dual-Channel Bonded
T
T
Characters Generated
Encoded data character on channel A
K28.5 fill character on channel A
Special character code on channel A
16-character word sync on channel A
Encoded data character on channel B
K28.5 fill character on channel B
Special character code on channel B
16-character word sync on channel B
0
0
1
1
X
X
X
X
0
1
0
1
0
1
0
1
Table 15. TX Modes 5 and 8, Quad-Channel Bonded
T
T
Characters Generated
Encoded data character on channel A
K28.5 fill character on channel A
Special character code on channel A
16-character word sync on channel A
Encoded data character on channel B
K28.5 fill character on channel B
Special character code on channel B
16-character word sync on channel B
Encoded data character on channel C
K28.5 fill character on channel C
Special character code on channel C
16-character word sync on channel C
Encoded data character on channel D
K28.5 fill character on channel D
Special character code on channel D
16-character word sync on channel D
0
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
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