參數(shù)資料
型號(hào)： CYP15G04K100V1
英文描述： Physical Layer Devices
中文描述： 物理層設(shè)備
文件頁(yè)數(shù)： 37/78頁(yè)
文件大?。?/td> 1555K
代理商： CYP15G04K100V1
CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 37 of 78
Configuration Parameters
Power-up Sequence Requirements
Upon power-up, all the outputs remain three-stated until all
the V
pins
have powered-up to the nominal voltage and
the part has completed configuration.
The part will not start configuration until V
, V
,
V
, V
, V
CCPLL
and V
CCPRG
have reached
nominal voltage.
V
CC
pins can be powered up in any order. This includes V
CC
,
V
CCIO
, V
CCJTAG
, V
CCCNFG
, V
CCPLL
and V
CCPRG
.
All V
s on a bank should be tied to the same potential
and powered up together.
All V
s (even the unused banks) need to be powered up
to at least 1.5V before configuration has completed.
Maximum ramp time for all V
CC
s should be 0V to nominal
voltage in 100 ms.
LVDIFF Inputs: REFCLK
±
V
DIFF [15]
V
IHHP
V
ILLP
V
COM [16]
3-Level Inputs
V
IHH
V
IMM
V
ILL
I
IHH
I
IMM
I
ILL
Differential CML Serial Outputs: OUTA1
±
, OUTA2
±
, OUTB1
±
, OUTB2
±,
OUTC1
±
, OUTC2
±
, OUTD1
±
, OUTD2
±
V
OHC
Output HIGH Voltage
(V
CC
referenced)
150
differential load
V
OLC
Output LOW Voltage
(V
CC
referenced)
150
differential load
V
ODIF
Output Differential Voltage
|(OUT+)
(OUT
)|
150
differential load
Differential Serial Line Receiver Inputs: INA1
±
, INA2
±
, INB1
±
, INB2
±
, INC1
±
, INC2
±
, IND1
±
, IND2
±
V
DIFF
Input Differential Voltage
|(IN+)
(IN
)|
V
IHE
Highest Input HIGH Voltage
V
ILE
Lowest Input LOW Voltage
I
IHE
Input HIGH Current
V
IN
= V
IHE
Max.
I
ILE
Input LOW Current
V
IN
= V
ILE
Min.
Miscellaneous
I
CC [17]
Power Supply Current
Freq.
= Max.
Notes:
14. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.
15. This is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0.
16. The common mode range defines the allowable range of REFCLK+ and REFCLK
(relative to the associated power rail) when
|(REFCLK+)
(REFCLK
)| = 0V. This marks the zero-crossing between the true and complement inputs as the signal switches between HIGH and LOW.
17. Maximum I
is measured with V
= MAX, RFEN = LOW, with all serial channels sending a constant alternating 01 pattern, and outputs unloaded. Typical
I
CC
is measured under similar conditions except with V
CC
= 3.3V, T
A
= 25
°
C.
Input Differential Voltage
Highest Input HIGH Voltage
Lowest Input LOW voltage
Common Mode Range
400
1.0
GND
1.0
V
CC
V
CC
mV
V
V
V
V
CC
0.4V
V
CC
1.2V
Three-Level Input HIGH Voltage
Three-Level Input MID Voltage
Three-Level Input LOW Voltage
Input HIGH Current
Input MID current
Input LOW current
Min.
≤
V
CC
≤
Max.
Min.
≤
V
CC
≤
Max.
Min.
≤
V
CC
≤
Max.
V
IN
= V
CC
V
IN
= V
CC
/2
V
IN
= GND
0.87 * V
CC
0.47 * V
CC
0.0
V
CC
V
V
V
μ
A
μ
A
μ
A
0.53 * V
CC
0.13 * V
CC
200
50
200
50
100
differential load
V
CC
0.85
V
CC
0.85
V
CC
1.1
V
CC
1.1
300
450
V
CC
0.2
V
CC
0.2
V
CC
0.7
V
CC
0.7
800
1200
V
V
V
V
100
differential load
100
differential load
mV
mV
100
1200
mV
V
CC
1.2
V
CC
2.0
V
CC
V
V
μ
A
μ
A
V
CC
1.45
1300
600
Typ.
1800
Max.
2000
Commercial
mA
Parameter
Description
Test Conditions
Min.
Max.
Unit
Parameter
Description
Min.
200
Units.
ns
t
RECONFIG
Reconfig
pin LOW time before it goes HIGH
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