參數(shù)資料
型號(hào)： CYP15G04K100V1
英文描述： Physical Layer Devices
中文描述： 物理層設(shè)備
文件頁(yè)數(shù)： 63/78頁(yè)
文件大小： 1555K
代理商： CYP15G04K100V1
CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 63 of 78
TXCTA[1:0]
TXCTB[1:0]
TXCTC[1:0]
TXCTD[1:0]
LVTTL Input,
synchronous,
sampled by the
selected TXCLKx
↑
or REFCLK
↑
[36]
Transmit Control. These inputs are captured on the rising edge of the transmit interface
clock (selected by TXCKSEL) and are passed to the encoder or transmit shifter. They
identify how the associated TXDx[7:0] characters are interpreted. When the encoder is
bypassed, these inputs are interpreted as data bits. When the encoder is enabled, these
inputs determine if the TXDx[7:0] character is encoded as Data, a Special Character
code, or replaced with other Special Character codes. See
Table 8
for details.
These signals are internal signals linking the SERDES block to the Logic block.
Transmit Data Inputs. These inputs are captured on the rising edge of the transmit
interface clock (selected by TXCKSEL) and passed to the encoder or transmit shifter.
When the encoder is enabled (TXMODE[1:0]
≠
LL), TXDx[7:0] specify the specific data
or command character to be sent.
These signals are internal signals linking the SERDES block to the Logic block.
Transmit Clock Phase Reset, active LOW. When LOW, the transmit Phase-Align Buffers
are allowed to adjust their data-transfer timing (relative to the selected input clock) to
allow clean transfer of data from the input register to the encoder or transmit shift reg-
ister. When TXRST is deasserted (HIGH), the internal phase relationship between the
associated TXCLKx and the internal character-rate clock is fixed and the device oper-
ates normally.
When configured for half-rate REFCLK sampling of the transmit character stream
(TNSXCKSEL = LOW and TXRATE = HIGH), assertion of TXRST is only used to clear
phase align buffer faults caused by highly asymmetric REFCLK periods or REFCLKs
with excessive cycle-to-cycle jitter.
During this alignment period, one or more characters may be added to or lost from all
the associated transmit paths as the transmit Phase-Align Buffers are adjusted.
TXRST must be sampled LOW by a minimum of two consecutive rising edges of TXN-
SCLKA (or one REFCLK
↑
) to ensure the reset operation is initiated correctly on all
channels.
This input is not interpreted when both TXCKSEL and TXRATE are LOW.
Transmit Path Clock and Clock Control
TXCKSEL
LVTTL
Static Control Input
transmit input register, for the transmit channel(s).
When LOW, all four input registers are clocked by REFCLK
↑
[36]
.
When HIGH, TXCLKA
↑
is used to clock data into the input register of each channel.
TXCLKO
LVTTL Output
Transmit Clock Output. This output clock is synthesized by the transmit PLL and oper-
ates synchronous to the internal transmit character clock. It operates at either the same
frequency as REFCLK, or at twice the frequency of REFCLK (as selected by TXRATE).
TXCLKO is always equal to the transmit VCO bit-clock frequency
÷
10. This output clock
has no direct phase relationship to REFCLK or any recovered character clock.
TXRATE
LVTTL Input,
Static Control input,
internal pull-down
PLL multiples REFCLK by 10 to generate the serial bit-rate clock. See
Table 17
for a list
of operating serial rates.
When REFCLK is selected for clocking of the receive parallel interfaces (RXCKSEL =
LOW), the TXRATE input also determines if the clock on the RXCLKA
+
and RXCLKC
+
outputs is a full or half-rate clock. When TXRATE = HIGH, these output clocks are half-
rate clocks and follow the frequency and duty cycle of the REFCLK input. When TXRATE
= LOW, these output clocks are full-rate clocks and follow the frequency and duty cycle
of the REFCLK input.
TXDA[7:0]
TXDB[7:0]
TXDC[7:0]
TXDD[7:0]
LVTTL Input,
synchronous,
sampled by the
selected TXCLKx
↑
or REFCLK
↑
[36]
TXRST
LVTTL Input, asyn-
chronous,
internal pull-up,
sampled by
TXCLKA
↑
or
REFCLK
↑
[36]
Transmit Clock Select. Selects the transmit clock source, used to write data into the
Transmit PLL Clock Rate Select. When TXRATE = HIGH, the Transmit PLL multiplies
REFCLK by 20 to generate the serial bit-rate clock. When TXRATE = LOW, the transmit
Notes:
36. When REFCLK is configured for half-rate operation (TXRATE = HIGH), these inputs are sampled (or the outputs change) relative to both the rising and falling
edges of REFCLK.
37. 3-Level select inputs are used for static configuration. They are ternary (not binary) inputs that make use of non-standard logic levels of LOW, MID, and HIGH.
The LOW level is usually implemented by direct connection to V
(ground). The HIGH level is usually implemented by direct connection to V
CC
(power). When
not connected or allowed to float, a 3-Level select input will self-bias to the MID level.
Frequency Agile PSI
Name
Function
Signal Description
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