參數(shù)資料
型號(hào)： CYP15G04K100V1
英文描述： Physical Layer Devices
中文描述： 物理層設(shè)備
文件頁(yè)數(shù)： 5/78頁(yè)
文件大小： 1555K
代理商： CYP15G04K100V1
CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 5 of 78
Functional Description
The Programmable Serial Interface (PSI) family is a point-to-
point or point-to-multipoint programmable communications
building block allowing the manipulation and transfer of data
over high-speed serial links at signaling speeds ranging from
200 Mbps to 1.5 and 2.5 Gbps per serial link. The PSI family
is designed to combine the high speed, predictable timing,
high density, low power, and ease-of-use of complex program-
mable logic devices (CPLDs) with the serializing/deserializing
(SERDES) capability of high-speed serial transceivers. The
family is divided into two groups: High-Speed PSI and Fre-
quency Agile PSI. Both groups have unique transceiver char-
acteristics that define the specific transceiver block operation
of a given PSI device.
The architecture of the device is based on logic block clusters
(LBC) and serial transceiver blocks that are connected by hor-
izontal and vertical routing channels. Each LBC features eight
individual logic blocks (LB) of 16 macrocells and two cluster
memory blocks. Adjacent to each LBC is a channel memory
block, which is externally accessible through the I/O interface.
Each transmit channel of the transceiver accepts parallel char-
acters, encodes each character for transport and converts it to
serial data. Each receive channel accepts serial data and con-
verts it to parallel data, decoding the data into characters and
presents these characters to the routing channels of the PSI
unit.
Frequency Agile Devices
The transceiver operation of the Frequency Agile Programma-
ble Serial Interface devices is self-contained in a single block.
It has separate transmit and receive PLLs and a clock and data
recovery (CDR) unit for flexible clocking. The transmit channel
accepts an 8-bit unencoded or 10-bit encoded input character
from the routing channels and passes the character to an elas-
ticity buffer. This character is then serialized and output on dual
differential transmission-line drivers at the required bit-rate.
The receive channel accepts a serial bit-stream from the two
differential line receivers. This bit-stream is deserialized and
an 8-bit unencoded or 10-bit encoded character is presented
to the routing channels in the PSI device. The block also fea-
tures Built-In Self Test (BIST) mode for simplified design de-
bugging.
Global Routing Description
The routing architecture in the PLD block of a PSI device is
made up of horizontal and vertical (H&V) routing channels.
These routing channels allow signals to move among I/Os,
logic blocks and memories. In addition to the horizontal and
vertical routing channels that interconnect the I/O banks,
channel memory blocks, transceiver blocks and logic block
clusters, each LBC contains a Programmable Interconnect
Matrix (PIM
), which is used to route signals among the logic
blocks and the cluster memory blocks in the LBC.
Figure 3
is a block diagram of the routing channels that inter-
face within the PSI architecture. The LBC is exactly the same
for every member of the PSI family.
Transceiver Block
Each transceiver block of a given PSI device will have one
serializer transmit path and one deserializer receive path op-
erating at a speed from 200 Mbps to 1.5 Gbps. The transceiver
block interfaces to the routing channels of the PSI device
through highly configurable datapath cells. For specific archi-
tecture and operation of the transceiver blocks please refer to
the Serial Transceiver Operation section (page 17).
Frequency Agile PSI Transceiver Blocks
Frequency Agile PSI devices include four or eight transceiver
blocks operating at 0.2 to 1.5 Gbps per channel. They use the
same reference clock.
The internal interfacing to the transceiver blocks of the device
occur through the port definition of the transceiver block. The
internal signals and their definition are described in the Pin and
Signal Description section (page 62).
Standard Datapath Cell
Figure 2
is a block diagram of the PSI datapath cell. The data-
path cell contains a three-state transmit buffer, a receive buff-
er, and a register that can be configured as an transmit or
receive register.
The transceiver enable (TE) can be selected from one of the
four global control signals or from one of two Output Control
Channel (OCC) signals. The transmit enable can be config-
ured as always enabled or always disabled or it can be con-
trolled by one of the remaining inputs to the mux. The selection
is done via a mux that includes V
CC
and GND as inputs.
One of the global clocks can be selected as the clock for the
datapath cell register. The clock mux output is an input to a
clock polarity mux that allows the transmit/receive register to
be clocked on either edge of the clock.
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