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參數(shù)資料
| 型號： | CYP15G04K100V1 |
| 英文描述： | Physical Layer Devices |
| 中文描述： | 物理層設備 |
| 文件頁數(shù)： | 68/78頁 |
| 文件大小： | 1555K |
| 代理商： | CYP15G04K100V1 |
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CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 68 of 78
MASTER
LVTTL Input,
static configuration
input
internal pull-down
Master Device Select. When LOW, the present device is configured as the master, and
BONDST[1:0] are outputs. When MASTER = HIGH, BONDST[1:0] are inputs.
MASTER is only interpreted when configured for quad channel bonding, and the receive
parallel interface is clocked by REFCLK
↑
.
All Channels Bonded Indicator. Active HIGH, wired AND. When HIGH, all receive chan-
nels have detected valid framing.
This output is driven only when all four channels are bonded together, and the receive
parallel interface is clocked by REFCLK
↑
.
Parallel Bond Inhibit. Active LOW. When asserted (LOW), this signal inhibits the adjust-
ment of character offsets in all receive channels if the Bonding Sequence has
not
been
detected in all bonded channels.
When HIGH, all channels that have detected the Bonding Sequence are allowed to align
their Receive Elasticity Buffer pipelines. For any channels to bond, the selected master
channel must be a member of the group.
When multiple devices are used together, the BOND_INH input on all parts must be
configured the same.
BOND_ALL
Bidirectional Open
Drain,
Internal pull-up
BOND_INH
LVTTL Input,
static configuration
input
Internal pull-up
JTAG Interface
TMS
LVTTL Input,
internal pull-up
LVTTL Input,
internal pull-down
Three-State
LVTTL Output
LVTTL Input,
internal pull-up
LVTTL Input,
internal pull-up
Test Mode Select. Used to control access to the JTAG Test Modes. If maintained high
for >5 TCLK cycles, the JTAG test controller is reset.
JTAG Test Clock
TCLK
TDO
Test Data Out. JTAG data output buffer which is High-Z while JTAG test mode is not
selected.
Test Data In. JTAG data input port.
TDI
TRSTZ
Test Port and Device Reset. Active LOW. Initializes the JTAG controller and all state
machines and counters in the device.
When asserted (LOW), this input asynchronously resets the JTAG test access port
controller.
When sampled LOW by the rising edge of REFLCK, this input resets the internal state
machines and sets the Elasticity Buffer pointers to a nominal offset. When the reset is
removed (TRSTZ sampled HIGH by REFCLK
↑
), the status and data outputs will be-
come deterministic in less than 16 REFCLK cycles.
The BISTLE, OELE, and RXLE latches will be reset by TRSTZ.
Power
V
CC
GND
V
CCIO0
V
CCIO1
V
CCIO2
V
CCIO3
V
CCIO4
V
CCIO5
V
CCIO6
V
CCIO7
V
CCJTAG
V
CCCNFG
V
CCPLL
V
CCPRG
Power
Ground
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
+3.3V Supply (operating voltage)
Signal and Power Ground
V
CC
for I/O bank 0
V
CC
for I/O bank 1
V
CC
for I/O bank 2
V
CC
for I/O bank 3
V
CC
for I/O bank 4
V
CC
for I/O bank 5 - Preset @ 3.3V TTL
V
CC
for I/O bank 6 - Preset @ 3.3V TTL
V
CC
for I/O bank 7 - Preset @ 3.3V TTL
V
CC
for JTAG pins
CC
for Configuration port
V
CC
for logic PLL
V
CC
for the Self-Boot
solution embedded boot PROM
Frequency Agile PSI
Name
Function
Signal Description
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