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| 型號： | CYNCP80192 |
| 英文描述： | Network Processing |
| 中文描述： | 網(wǎng)絡(luò)處理 |
| 文件頁數(shù)： | 31/42頁 |
| 文件大?。?/td> | 679K |
| 代理商： | CYNCP80192 |
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CYNCP80192
Document #: 38-02043 Rev. *B
Page 31 of 42
16.0
Electrical Characteristics
This section describes the electrical specifications, capacitance, operating conditions, DC characteristics, and AC timing param-
eters for the NDC (see
Table 16-1
,
Table 16-2
,
Table 16-3
,
Table 16-4
, and
Table 16-5
).
Table 16-1. Electrical Characteristics
Parameter
Description
Test Conditions
0 < V
IN
< V
DDQ
0 < V
OUT
< V
DDQ
8 mA, V
DDQ
= 3.3V
4 mA, V
DDQ
= 3.3V
Min.
–10
–10
Max.
10
10
0.4
Unit
uA
uA
V
V
mA
mA
I
LI
I
LO
V
OL
V
OH
I
CC
_core
I
CC
_IO
Table 16-2. Capacitance
Input Leakage Current
Output Leakage Current
[9]
Output Low Voltage
Output High Voltage
2.5 V Supply Current
[10]
3.3 V Supply Current
2.4
TBD
TBD
Parameter
Description
Max.
TBD
TBD
Unit
pF
[11]
pF
[12]
C
IN
C
OUT
Table 16-3. Operating Conditions
Input Capacitance
Output Capacitance
Parameter
V
DDQ
V
DD
V
IH
V
IL
T
A
Description
Min.
3.14
2.37
2.0
–0.3
0
–5%
Max.
3.45
2.63
V
DD
+0.3
0.8
70
+5%
Unit
V
V
V
V
oC
Operating Voltage for IO
Operating Supply Voltage
Input High Voltage
[13]
Input Low Voltage
[14]
Ambient Operating Temperature
Supply Voltage Tolerance
Table 16-4. AC Timing Parameters for Pipelined ZBT SSRAM and SyncBurst SSRAM
Parameter
T
CLK
T
CKHI
T
CKLO
T
SA
T
HA
T
CKOV
Description
Test Conditions
Load (pF)
CYNPC80192–100 CYNPC80192–83
Min.
Max.
100
4.0
4.0
2.5
1.5
8.0
Unit
MHz
ns
ns
ns
ns
ns
Min.
Max.
83
CLK period: max frequency
CLK high pulse; worst-case 40%–60% duty cycle
[15]
CLK low pulse; worst-case 40%–60% duty cycle
[15]
Set-up Time to CLK rising edge
[16]
Hold Time to CLK rising edge
[17]
Clock to output valid (Network Processor
Interface)
Clock to CLK2X delay
Clock to PHS_L delay
Clock to output valid (NSE Interface)
Clock to SCLK delay
Clock to output valid (SDATA)
Clock to output in Low-Z
Clock to output in High-Z
4.8
4.8
3.0
1.5
30
9.0
T
CK2X
T
CLKPHSL
T
CKSE
T
SCK
T
CKSD
T
CKOLZ
T
CKOHZ
Notes:
9.
Applies only for outputs in three-state.
10. Average operating current at maximum frequency. Transient peak currents may exceed these values.
11.
f = 1 MHz, V
IN
= 0V.
12. f = 1 MHz, V
– 0V.
13. Maximum allowable applies to overshoot only (V
DDQ
is 3.3V supply).
14. Minimum allowable applies to undershoot only.
15. 1. T
and T
duty-cycle values are based on 20–80% signal levels.
16. 2. Set-up time for ADR, CLK enable, data, Read/Write, CE, and byte Write enable.
17. 3. Hold time for ADR, CLK enable, data, Read/Write, CE, and byte Write enable.
3.5
6
9
5
10
4.0
7
11
6
12
ns
Ns
ns
ns
ns
ns
ns
40
20
3
3
6
7
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