
CYNCP80192
Document #: 38-02043 Rev. *B
Page 2 of 42
CONTENTS
1.0 OVERVIEW ......................................................................................................................................5
2.0 FEATURES ......................................................................................................................................6
3.0 FUNCTIONAL DESCRIPTION .........................................................................................................7
3.1 Configuration Registers ..............................................................................................................7
3.2 Operating Registers ....................................................................................................................7
3.3 Pipeline and Table Management and Bus Protocol Conversion Logic .......................................7
3.4 NSE Interface ..............................................................................................................................7
3.5 Associative SSRAM Interface .....................................................................................................7
4.0 SIGNAL DESCRIPTION ...................................................................................................................8
5.0 CLOCKS .........................................................................................................................................11
6.0 REGISTERS ...................................................................................................................................12
6.1 Coprocessor Interface Register ................................................................................................12
6.2 Configuration and Status Registers ..........................................................................................12
7.0 OPERATING REGISTERS .............................................................................................................15
7.1 Address Mapping ......................................................................................................................15
7.2 Context Descriptor Organization ...............................................................................................16
7.3 Context Descriptor Commands .................................................................................................16
8.0 NDC SUBSYSTEM POWER-UP INITIALIZATION PROCEDURE ................................................23
9.0 ZBT PIPELINED SSRAM INTERFACE MODE .............................................................................24
10.0 ZBT FLOWTHROUGH SSRAM INTERFACE MODE ..................................................................25
11.0 SYNCBURST PIPELINED SSRAM INTERFACE (EARLY WRITE) ............................................26
12.0 SYNCBURST PIPELINED SSRAM INTERFACE MODE (LATE WRITE) ...................................27
13.0 APPLICATION INFORMATION ...................................................................................................28
14.0 INFORMATION ON EXTERNAL TRANSCEIVERS ....................................................................29
15.0 JTAG (1149.1) TESTING .............................................................................................................30
16.0 ELECTRICAL CHARACTERISTICS ............................................................................................31
17.0 ORDERING INFORMATION ........................................................................................................39
18.0 PACKAGE DRAWINGS ...............................................................................................................40