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參數(shù)資料
| 型號(hào)： | CYNCP80192 |
| 英文描述： | Network Processing |
| 中文描述： | 網(wǎng)絡(luò)處理 |
| 文件頁數(shù)： | 29/42頁 |
| 文件大小： | 679K |
| 代理商： | CYNCP80192 |
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CYNCP80192
Document #: 38-02043 Rev. *B
Page 29 of 42
14.0
Information on External Transceivers
As more NSEs are added to the DQ bus, the capacitive load on the bus increases, reducing the bus speed. CYNSE80192 gets
around this by using external transceivers, and provides a glueless support to add the transceivers (Phillips 74ALVT16652)
between a bank of NSEs and the CYNPC80192 (see
Figure 14-1
).
The XVER_0, XVER_1, and XVER_2 are electrically buffered versions of the same logical signal in the CYNPC80192 device.
The XVER_0_L, XVER_1_L, and XVER_2_L are also electrically buffered versions of the same logical signal in the CYNPC80192
device. Multiple copies of these signals are provided in order to increase the ability of the signal to drive many transceiver devices
of eight-bit width.
Figure 14-2
shows one example of the distribution of signals driving the transceivers.
CLK (System Clock)
XVER_0
XVER_0_L
Transceivers
Transceivers
Transceivers
C
XVER_1
XVER_1_L
XVER_2
XVER_2_L
Figure 14-1. Use of Transceiver Enables
Transceivers
CYNCP80192
NSEs
SSRAM
Figure 14-2. Transceiver Connected Between CYNPC80192 and CYNSE70XXX Devic-
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