- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369679 > CYNCP80192 Network Processing PDF資料下載
參數(shù)資料
| 型號： | CYNCP80192 |
| 英文描述： | Network Processing |
| 中文描述： | 網(wǎng)絡(luò)處理 |
| 文件頁數(shù)： | 27/42頁 |
| 文件大?。?/td> | 679K |
| 代理商： | CYNCP80192 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當(dāng)前第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁
CYNCP80192
Document #: 38-02043 Rev. *B
Page 27 of 42
12.0
SyncBurst Pipelined SSRAM Interface Mode (Late Write)
The ADR and control signals (R/W_L, BW_L[7:0], CE_L, CE2, CE2_L) are sampled on a CLK edge. For Write cycles, the data
is sampled one cycle later; for Read cycles, the data is available to the processor one cycle later. Both Write- and Read-cycle
latency is one cycle, and there is no gap required between Read and Write operation. Every cycle is available for the network
processor(s) for full utilization of the bus bandwidth. See
Figure 12-1
.
Note
. BWE_L is not used in this mode and should be tied
inactive.
CLK
1
2
3
4
5
6
7
ADR[9:0]
A1
A2
BW_L[7:0]
DATA[63:0]
D1
Q2
D3
Q4
CE_L
CE_2
R/W_L
STRB
CPID[7:0]
CPID
Write
Read
NOP
Read
8
Write
A4
A5
A3
Q5
Figure 12-1. SyncBurst Pipelined SSRAM Interface (Late Write)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYNSE70032 | Network Processing |
| CYNSE70128 | Network Processing |
| CYNSE70256 | Network Processing |
| CZET101 | Clock Driver |
| CZEU101 | Quad Peripheral Driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYNPC80192-BGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Network Database Coprocessor |
| CYNSE10128 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Ayama⑩ 10000 Network Search Engine |
| CYNSE10128-083FGCI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Ayama⑩ 10000 Network Search Engine |
| CYNSE10128-100FGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Ayama⑩ 10000 Network Search Engine |
| CYNSE10128-133FGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Ayama⑩ 10000 Network Search Engine |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。