參數(shù)資料
型號： CYNCP80192
英文描述： Network Processing
中文描述： 網(wǎng)絡(luò)處理
文件頁數(shù)： 12/42頁
文件大?。?/td> 679K
代理商： CYNCP80192
CYNCP80192
Document #: 38-02043 Rev. *B
Page 12 of 42
6.0
Registers
6.1
The network processor(s) access the NDC using the coprocessor (SSRAM) interface. The NDC has a CFG and status registers
area and an operating registers area, as shown in
Table 6-1
.
Coprocessor Interface Register
The CFG area shown in
Table 6-2
is used for programming the NDC via a 64-bit CFG register.
[5]
6.2
Configuration and Status Registers
6.2.1
The 64-bit CFG register contains the following fields, as shown in
Table 6-3
.
Configuration Register
SRST
. This active high bit resets the state of the device. The reset bit will be active for 32 CLK cycles and will be automatically
cleared after the reset has taken effect.
Table Size (TLSZ)
. This determines the NSE CFG for the specific table size.
[6]
Latency of Hit Signals (HLAT)
. This determines the data access latency of associated data SSRAM.
[7]
CPCFG
. This field sets the width of the processor and context IDs that will be driven on the CPID bus after the completion of the
operation. The contents of the CPID bus are generated by concatenating LSBs of the processor ID and the LSBs of the context ID.
00: CPID[7:0] = {processor ID[2:0], context ID[4:0]}.
01: CPID[7:0] = {processor ID[3:0], context ID[3:0]}.
10: CPID[7:0] = {processor ID[4:0], context ID[2:0]}.
11: Reserved.
Notes:
4.
5.
The resulting registers of the context descriptors are Read-only.
Once the NDC is configured, the network processors will use the operating registers area to configure the NSEs, initialize and manage the protocol layer tables,
and perform searches through such tables.
Though the NDC does not program the NSE with this information, the coprocessor uses it to determine the duration of operations such as Search and Learn.
(More details on this field can be found in the data sheets for CYNSE70XXX NSEs.)
Though the NDC does not program the NSE with this information, the coprocessor uses it to determine the duration of operations such as Search and Read
from the SSRAMs. (More details on this field can be found in the data sheet on CYNSE70XXX NSEs.)
6.
7.
Table 6-1. Register Partitions for Coprocessor Access
Address
0–511
Abbreviation
CFG and Status
Registers
Type
R/W
Description
These registers are for configuring the NDC (Read/Write), reporting the
error code in the status register (Read-only), setting up the mask register
for asserting INTR (Read/Write), and obtaining information on the device
(Read-only).
Dynamic access for searches and table management happens through this
area of the coprocessor address space.
[4]
512–1023
ADR[9] = 1
Operating Registers
R/W
Table 6-2. Configuration and Status Registers Area
Address
0–1
2–3
4–5
6–7
8–9
10–511
Configuration and Status Registers Area
CFG Register
Error, Status Registers (Read-only)
Mask Registers
Reserved
Information Registers (Read-only)
Reserved
Table 6-3. Configuration Register
Configuration Register [63:0]
9
Search Result
Bit in Data
Field
ADR
0–1
63–12
Reserved
11
10
8
7–6
5–3
HLAT
2–1
TLSZ
0
External
Transceiver
Present
INTR_Polarity
SSRAM
Present
CPCFG
SRST
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CYNPC80192-BGC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Network Database Coprocessor
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CYNSE10128-100FGC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Ayama⑩ 10000 Network Search Engine
CYNSE10128-133FGC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Ayama⑩ 10000 Network Search Engine
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